EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 370

• Manufacturer Part Number: EP1S10F780I6N
• Description: IC STRATIX FPGA 10K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F780I6N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 426
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

TriMatrix Memory
2–2
Stratix Device Handbook, Volume 2
Notes to
(1)
(2)
Performance
Total RAM bits (including parity bits)
Configurations
Parity bits
Byte enable
Single-port memory
Simple dual-port memory
True dual-port memory
Embedded shift register
ROM
FIFO buffer
Simple dual-port mixed width support
True dual-port mixed width support
Memory initialization file (.mif)
Mixed-clock mode
Power-up condition
Register clears
Same-port read-during-write
Mixed-port read-during-write
Table 2–1. Summary of TriMatrix Memory Features
The rden register on the M512 memory block does not have a clear port.
On the M4K block, asserting the clear port of the rden and byte enable registers drives the output of these registers
high.
Table
Feature
2–1:
Outputs set to
Outputs cleared
Input and output
registers
New data available at
positive clock edge
unknown or old data
M512 Block
319 MHz
512 × 1
256 × 2
128 × 4
32 × 16
32 × 18
64 × 8
64 × 9
(1)
576
v
v
v
v
v
v
v
v
v
Outputs cleared
Input and output
registers
New data available at
positive clock edge
Outputs set to
unknown or old data
M4K Block
290 MHz
256 × 16
256 × 18
128 × 32
128 × 36
512 × 8
512 × 9
4K × 1
2K × 2
1K × 4
4,608
(2)
v
v
v
v
v
v
v
v
v
v
v
v
Outputs unknown
Output registers
New data available at
positive clock edge
Unknown output
Altera Corporation
M-RAM Block
287 MHz
32K × 16
32K × 18
16K × 32
16K × 36
4K × 128
4K × 144
589,824
64K × 8
64K × 9
8K × 64
8K × 72
v
v
v
v
v
v
v
v
v
July 2005