EP3C16F256C7N Altera, EP3C16F256C7N Datasheet - Page 8

• Manufacturer Part Number: EP3C16F256C7N
• Description: IC CYCLONE III FPGA 16K 256FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C16F256C7N

• Number Of Logic Elements/cells: 15408
• Number Of Labs/clbs: 963
• Total Ram Bits: 516096
• Number Of I /o: 168
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 15408
• # I/os (max): 168
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 15408
• Ram Bits: 516096
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2463

Page 8
Early System Planning
To build a simpler system, the active configuration scheme provides a one-chip
solution configuration where only a serial configuration device is required for the AS
configuration scheme or a parallel flash memory is required for the AP configuration
scheme. The passive configuration scheme provides a two-chip solution
configuration. If your system already contains an external intelligent host or a
microprocessor, you can utilize it with a flash memory to perform the passive
configuration scheme such as the PS or FPP.
f
For more information on the configuration scheme selection, refer to the
Configuration
Center. This web page includes a link to the configuration guidelines
that provide an overview of Altera FPGA configuration schemes and a general
comparison of the schemes to guide you in choosing the one that best suits your
design requirements.
All configuration schemes use a configuration device, a download cable or an external
controller (for example, a MAX
®
II device or microprocessor). The AS and AP schemes
use an external flash memory, such as serial configuration device or a supported flash
memory, respectively. The PS and JTAG schemes use either an external controller or a
download cable. The FPP scheme uses an external controller.
When choosing the configuration scheme that best suits your system requirements,
you may also want to consider the configuration time. Configuration time varies for
different configuration schemes and depends on the configuration file size,
configuration data width, frequency of the driving clock, and flash access time.
The AP configuration scheme offers the fastest configuration time among the
supported configuration schemes in a Cyclone III device. The speedup in the
configuration time is mainly due to the 16-bit wide parallel data bus which is used to
retrieve data from the flash. However, a 24-bit address bus is required to connect the
Cyclone III device to the address bus of the flash memory. In other words, 40 pins of
your Cyclone III device and the flash memory would be occupied for the address bus
and data transfer. Comparatively, the FPP takes only 8 pins of your Cyclone III device
and the flash memory device for the data transfer and does not require an address
bus. Although the configuration of the FPP is not relatively as fast as the configuration
of the AP but this scheme provides faster configuration time compared to any serial
configuration scheme such as the AS and PS.
For the active configuration schemes such as the AS and AP, the DCLK is an output
from the Cyclone III device that provides the timing for the configuration interface.
The maximum DCLK frequency for the AS and AP is 40 MHz. In the PS and FPP
configuration, the DCLK is the clock input that is used to clock data from an external
source into the target Cyclone III device. Data is latched into the device on the rising
edge of the DCLK. In other words, you are able to monitor the DCLK frequency to
control the configuration time in the passive configuration scheme by varying the
clock from the external source. For the PS, the maximum DCLK frequency is 133 MHz
and for the FPP, the maximum DCLK frequency is 100 MHz.
Table 4
simplifies the general comparison of the supported configuration schemes in
Cyclone III.
© November 2008 Altera Corporation