EP3C16F256C7N Altera, EP3C16F256C7N Datasheet - Page 6

• Manufacturer Part Number: EP3C16F256C7N
• Description: IC CYCLONE III FPGA 16K 256FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C16F256C7N

• Number Of Logic Elements/cells: 15408
• Number Of Labs/clbs: 963
• Total Ram Bits: 516096
• Number Of I /o: 168
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 15408
• # I/os (max): 168
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 15408
• Ram Bits: 516096
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2463

Page 6
Planning and Selecting Configuration Scheme
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External Memory Interface
Cyclone III devices support interfaces to the DDR2 SDRAM, DDR SDRAM, and
QDRII SRAM. Depending on device density and package, specific side of I/O bank
may support up to ×36 mode of memory interface. Supported modes in the
Cyclone III devices are ×8, ×9, ×16, ×18, ×32, and ×36 modes. Use the Pin Planner tool
to assist you in determining and making pin assignments for the memory interface.
In general, choose the top or bottom I/O banks instead of the side I/O banks to
achieve a higher clock rate for the external memory interfaces. The Cyclone III devices
support external memory interfaces up to 200 MHz.
For more information about the DDR/DDR2 and QDRII pads placement, refer to the
Cyclone III Device I/O Feature
For more information about the recommended design flow to implement the
DDR2 SDRAM memory interface with Cyclone III devices, refer to
Guidelines for Implementing DDR and DDR2 SDRAM Interfaces in Cyclone III Devices.
For a complete table of the maximum clock rate support across all speed grades for
every memory standard, refer to the
the Cyclone III Device Handbook.
Pin-Out Files
The Cyclone III pin-out files contain information about the location for all the pins of
the devices, according to package. For the I/O pins, you can also know which I/O
bank and the V
description for the dedicated and multi-purpose pins. The pin-out files help designer
to determine the I/O pins to be used when creating the design as well as when
designing the board. Apart from I/O pins, the location of dedicated and
multi-purpose pins is also important during the board design stage.
To obtain device pin-outs for Cyclone III devices, refer to the
the Literature section of the Altera website (www.altera.com).
Choose your device configuration method early to allow system and board designers
to determine if any additional devices are required for your system. Your board layout
depends on the configuration method that you plan to use for the programmable
device, because different schemes require different connections.
For board design guidelines related to configuration pins, refer to
Considerations”.
REF
group the pins belong to. The pin-out files also contain the
chapter in volume 1 of the Cyclone III Device Handbook.
External Memory Interfaces
© November 2008 Altera Corporation
Device Pin-Outs
chapter in volume 1 of
“Board Design
AN 445: Design
Early System Planning
page of