EP3C16F256C7N Altera, EP3C16F256C7N Datasheet - Page 5

• Manufacturer Part Number: EP3C16F256C7N
• Description: IC CYCLONE III FPGA 16K 256FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C16F256C7N

• Number Of Logic Elements/cells: 15408
• Number Of Labs/clbs: 963
• Total Ram Bits: 516096
• Number Of I /o: 168
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 15408
• # I/os (max): 168
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 15408
• Ram Bits: 516096
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2463

Early System Planning
Table 3. Selection Criteria for Each I/O Signaling Type (Part 2 of 2)
© November 2008 Altera Corporation
Differential (2),
Notes to
(1) Differential voltage-referenced standards can only be used for clocking. These I/O standards are only supported on the GCLK and PLL_OUT
(2) Side I/O banks support dedicated differential buffers. Top and bottom I/O banks support differential signaling with an additional resistor network
(3) For details on the guidelines and considerations of the high-speed LVDS interface implementation in a Cyclone III device, refer to
I/O Signaling Type
pins.
on the transmitter side.
Design Guidelines for Implementing LVDS Interfaces in Cyclone Series Devices.
Table
f
3:
1
(3)
Flexible I/O Banks
Simultaneous support of various I/O standards is possible with efficient I/O
groupings in banks. Each bank must be supplied with one V
is powered up individually by the VCCIO pins of that particular bank and is
independent of the V
increased flexibility to be used with multi-voltage systems. Note that an output buffer
does not meet the configured I/O standard specification if the V
recommended operating range according to the Cyclone III device datasheet for the
I/O standard.
Although there can only be one V
permit additional input signaling capabilities.
For more information about the acceptable input and output levels, refer to the
Cyclone III Device I/O Features
Each Cyclone III I/O bank has a VREF bus to accommodate voltage-referenced I/O
standards. Multiple VREF pins within an I/O bank feed the common VREF bus. Each
bank can only have a single V
given time. V
HSTL I/O standards) to determine logic threshold. It is therefore important for VREF
to be noise-free.
Follow pad placement guidelines in the
volume 1 of the Cyclone III Device Handbook to minimize noise coupling onto the
reference voltage.
Voltage deviation on the VREF pin can affect the threshold sensitivity for the input
operation. If a voltage referenced input is not utilized for a V
released automatically by the Quartus II software for use as an I/O pin but with
higher pin capacitance due to the power bus loading effects.
Superior speed (up to 840 Mbps), lower swing voltage
and increased noise immunity with common mode
noise rejection capability.
REF
is used as a reference voltage for voltage-referenced inputs (SSTL and
Performance
CCIO
of other I/O banks. Eight I/O banks are offered for
chapter in volume 1 of the Cyclone III Device Handbook.
CCIO
CCIO
voltage level and a single V
Selection Criteria
voltage per I/O bank, Cyclone III devices
Cyclone III Device I/O Features
Low, with reduced physical traces and
I/O resources by implementing
serialization/deserialization (SERDES)
logic to replace parallel data
transmission.
REF
CCIO
REF
group, the VREF pin is
CCIO
level. Each I/O bank
voltage level at a
Cost
is out of the
chapter in
AN 479:
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