EP3C16F256C7N Altera, EP3C16F256C7N Datasheet - Page 39

• Manufacturer Part Number: EP3C16F256C7N
• Description: IC CYCLONE III FPGA 16K 256FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C16F256C7N

• Number Of Logic Elements/cells: 15408
• Number Of Labs/clbs: 963
• Total Ram Bits: 516096
• Number Of I /o: 168
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 15408
• # I/os (max): 168
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 15408
• Ram Bits: 516096
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2463

Design and Compilation
I/O Considerations
© November 2008 Altera Corporation
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Architectural Optimization
Use specific device architecture features to reduce power consumption. For example,
use the dedicated DSP block available in the Cyclone III device in place of LEs to
perform arithmetic-related functions; build large shift registers from RAM-based
FIFO buffers instead of building the shift registers from the LE registers.
Cyclone III devices offer increased system integration with enhancements in I/O
flexibility and improvements in features. I/O capabilities of the FPGA device, board
layout guidelines, and signal integrity concerns significantly influence pin location
decisions and other types of assignments for each of your design pins. You can
optimize I/O resources for performance and cost while avoiding undesirable signal
issues with the tools and taking into account considerations described in this section.
I/O Tools
I/O design flow includes creating pin-related assignments and validating them
against pin placement guidelines. Use the Pin Planner and Assignment Editor tools in
the Quartus II software to help you through the pin-related assignment creation and
editing. I/O Assignment Analysis helps you to check the legality of the pin
assignments. The following subsections discuss the tools used to create and edit
pin-related assignments.
Pin Planner
The Pin Planner is used to create and edit pin-related assignments. Use the Pin
Planner Package View to make pin location and other assignments using a device
package view instead of pin numbers. With the Pin Planner, you can visually identify
I/O banks, V
pins in the Package View helps you to minimize signal breakout congestion on board
layout when making pin location assignments.
Complementing the Pin Planner is the Pad View window, which displays the pads in
the order around the silicon die. Package pins are connected to pads located on the
perimeter of the top metal layer of the silicon die. Note the pad location where your
pins were assigned, because some pin placement rules describe pad placement
restrictions. Use the Pad View window to guide your pin placement decisions to
maintain good signal integrity for the interface in your design.
The Pin Migration View in the Pin Planner tool shows the pins that will change
function in a migration device if you select one or more migration devices for your
project. It helps you to identify the differences in pins which can exist between
migration devices.
For details about using the Package View, Pad View, and Pin Migration View in the
Pin Planner tool, refer to the Using the Pin Planner section of the
chapter in volume 2 of the Quartus II Handbook.
Assignment Editor
While the Pin Planner provides an intuitive graphical representation of the targeted
device, the Assignment Editor provides a spreadsheet-like interface that allows you to
create and change all pin-related assignments.
REF
groups, and differential pin pairings. The visual representation of
I/O Management
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