EP3C5F256I7N Altera, EP3C5F256I7N Datasheet - Page 48
![IC CYCLONE III FPGA 5K 256 FBGA](/photos/6/70/67063/544-256-fbga_sml.jpg)
EP3C5F256I7N
Manufacturer Part Number
EP3C5F256I7N
Description
IC CYCLONE III FPGA 5K 256 FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C5F256I7N.pdf
(274 pages)
Specifications of EP3C5F256I7N
Number Of Logic Elements/cells
5136
Number Of Labs/clbs
321
Total Ram Bits
423936
Number Of I /o
182
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
5136
# I/os (max)
182
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
5136
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2558
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C5F256I7N
Manufacturer:
ALTERA32
Quantity:
1 608
Part Number:
EP3C5F256I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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3–12
Cyclone III Device Handbook, Volume 1
Table 3–4
Table 3–4. Cyclone III Device Family M9K Block Mixed-Width Configurations (True Dual-Port
Mode)
In true dual-port mode, M9K memory blocks support separate wren and rden
signals. You can save power by keeping the rden signal low (inactive) when not
reading. Read-during-write operations to the same address can either output “New
Data” at that location or “Old Data”. To choose the desired behavior, set the
Read-During-Write option to either New Data or Old Data in the RAM MegaWizard
Plug-In Manager in the Quartus II software. For more information about this
behavior, refer to
In true dual-port mode, you can access any memory location at any time from either
port A or port B. However, when accessing the same memory location from both
ports, you must avoid possible write conflicts. When you attempt to write to the same
address location from both ports at the same time, a write conflict happens. This
results in unknown data being stored to that address location. There is no conflict
resolution circuitry built into the Cyclone III device family M9K memory blocks. You
must handle address conflicts external to the RAM block.
8192
4096
2048
1024
512
1024
512
Read Port
× 16
× 18
× 1
× 2
× 4
× 8
× 9
lists the possible M9K block mixed-port width configurations.
8192
v
v
v
v
v
—
—
“Read-During-Write Operations” on page
× 1
4096
v
v
v
v
v
—
—
× 2
2048
v
v
v
v
v
—
—
× 4
Chapter 3: Memory Blocks in the Cyclone III Device Family
Write Port
1024
v
v
v
v
v
—
—
× 8
512
© December 2009 Altera Corporation
v
v
v
v
v
—
—
× 16
3–16.
1024
v
v
—
—
—
—
—
× 9
Memory Modes
512
—
—
—
—
—
v
v
× 18
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