EP3C5F256I7N Altera, EP3C5F256I7N Datasheet - Page 147
![IC CYCLONE III FPGA 5K 256 FBGA](/photos/6/70/67063/544-256-fbga_sml.jpg)
EP3C5F256I7N
Manufacturer Part Number
EP3C5F256I7N
Description
IC CYCLONE III FPGA 5K 256 FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C5F256I7N.pdf
(274 pages)
Specifications of EP3C5F256I7N
Number Of Logic Elements/cells
5136
Number Of Labs/clbs
321
Total Ram Bits
423936
Number Of I /o
182
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
5136
# I/os (max)
182
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
5136
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2558
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C5F256I7N
Manufacturer:
ALTERA32
Quantity:
1 608
Part Number:
EP3C5F256I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 8: External Memory Interfaces in the Cyclone III Device Family
Cyclone III Device Family Memory Interfaces Pin Support
Table 8–1. Cyclone III Device DQS and DQ Bus Mode Support for Each Side of the Device (Part 1 of 4)
© January 2010 Altera Corporation
EP3C5
EP3C10
Device
144-pin
164-pin MBGA
256-pin FineLine
BGA/256-pin Ultra
FineLine BGA
144-pin EQFP
164-pin MBGA
256-pin FineLine
BGA/256-pin Ultra
FineLine BGA
In the ×9, ×18, and ×36 modes, a pair of complementary DQS pins (CQ and CQ#)
drives up to 9, 18, or 36 DQ pins, respectively, in the group, to support one, two, or
four parity bits and the corresponding data bits. The ×9, ×18, and ×36 modes support
the QDR II memory interface. CQ# is the inverted read-clock signal which is
connected to the complementary data strobe (DQS or CQ#) pin. You can use any
unused DQ pins as regular user I/O pins if they are not used as memory interface
signals.
Table 8–1
Cyclone III device only.
Package
EQFP(1)
(1)
(1)
(1)
(1)
(1)
lists the number of DQS or DQ groups supported on each side of the
Left
Right
Top
Bottom (3),
Left
Right
Top
Bottom (3),
Left (4),
Right (4),
Top
Bottom
Left
Right
Top
Bottom (3),
Left
Right
Top
Bottom (3),
Left (4),
Right (4),
Top
Bottom
(2)
(2)
(2)
(2)
Side
(5)
(5)
(6)
(6)
(4)
(4)
(4)
(4)
Number
Groups
×8
0
0
1
1
0
0
1
1
1
1
2
2
0
0
1
1
0
0
1
1
1
1
2
2
Number
Groups
×9
0
0
0
0
0
0
0
0
1
1
2
2
0
0
0
0
0
0
0
0
1
1
2
2
Number
Groups
×16
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
Cyclone III Device Handbook, Volume 1
Number
Groups
×18
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
Number
Groups
×32
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Number
Groups
×36
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8–3