EP3C5F256I7N Altera, EP3C5F256I7N Datasheet - Page 212
![IC CYCLONE III FPGA 5K 256 FBGA](/photos/6/70/67063/544-256-fbga_sml.jpg)
EP3C5F256I7N
Manufacturer Part Number
EP3C5F256I7N
Description
IC CYCLONE III FPGA 5K 256 FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C5F256I7N.pdf
(274 pages)
Specifications of EP3C5F256I7N
Number Of Logic Elements/cells
5136
Number Of Labs/clbs
321
Total Ram Bits
423936
Number Of I /o
182
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
5136
# I/os (max)
182
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
5136
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2558
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C5F256I7N
Manufacturer:
ALTERA32
Quantity:
1 608
Part Number:
EP3C5F256I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
9–52
Cyclone III Device Handbook, Volume 1
1
Cyclone III device family has dedicated JTAG pins that function as JTAG pins. You
can perform JTAG testing on Cyclone III device family before, during, and after
configuration. Cyclone III device family supports the BYPASS, IDCODE, and SAMPLE
instructions during configuration without interrupting configuration. All other JTAG
instructions can only be issued by first interrupting configuration and
reprogramming I/O pins using the ACTIVE_DISENGAGE and CONFIG_IO
instructions.
The CONFIG_IO instruction allows I/O buffers to be configured using the JTAG port
and when issued after the ACTIVE_DISENGAGE instruction interrupts configuration.
This instruction allows you to perform board-level testing prior to configuring the
Cyclone III device family or waiting for a configuration device to complete
configuration. Prior to issuing the CONFIG_IO instruction, you must issue the
ACTIVE_DISENGAGE instruction. This is because in Cyclone III device family, the
CONFIG_IO instruction does not hold nSTATUS low until reconfiguration, so you
must disengage the active configuration mode controller when active configuration is
interrupted. The ACTIVE_DISENGAGE instruction places the active configuration
mode controllers in an idle state prior to JTAG programming. Additionally, the
ACTIVE_ENGAGE instruction allows you to re-engage a disengaged active
configuration mode controller.
You must follow a specific flow when executing the CONFIG_IO,
ACTIVE_DISENGAGE, and ACTIVE_ENGAGE JTAG instructions in Cyclone III device
family. For more information about the instruction flow, refer to
on page
The chip-wide reset (DEV_CLRn) and chip-wide output enable (DEV_OE) pins on
Cyclone III device family do not affect JTAG boundary-scan or programming
operations. Toggling these pins does not affect JTAG operations (other than the usual
boundary-scan operation).
When designing a board for JTAG configuration, consider the dedicated configuration
pins.
Table 9–16
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
9–61.
lists how these pins must be connected during JTAG configuration.
© December 2009 Altera Corporation
“JTAG Instructions”
Configuration Features