XC5VLX110-1FFG676C Xilinx Inc, XC5VLX110-1FFG676C Datasheet - Page 211

• Manufacturer Part Number: XC5VLX110-1FFG676C
• Description: IC FPGA VIRTEX-5 110K 676FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX110-1FFG676C

• Total Ram Bits: 4718592
• Number Of Logic Elements/cells: 110592
• Number Of Labs/clbs: 8640
• Number Of I /o: 440
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 676-BBGA, FCBGA
• No. Of Logic Blocks: 17280
• No. Of Gates: 110000
• Family Type: Virtex-5 LX
• No. Of Speed Grades: 1
• No. Of I/o's: 440
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1557

CLB Primitives
Table 5-11: Single-Port, Dual-Port, and Quad-Port Distributed RAM
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
RAM128X1D
RAM128X1S
RAM256X1S
RAM32X1D
RAM64X1D
RAM32X1S
RAM64X1S
RAM32M
RAM64M
Primitive
Distributed RAM Primitives
•
•
More information on the CLB primitives are available in the software libraries guide.
Seven primitives are available; from 32 x 2 bits to 256 x 1 bit. Three primitives are single-
port RAM, two primitives are dual-port RAM, and two primitives are quad-port RAM, as
shown in
The input and output data are 1-bit wide (with the exception of the 32-bit RAM).
Figure 5-32
primitives. The A, ADDR, and DPRA signals are address buses.
At time T
D input of the slice register. This is reflected on any of the AQ/BQ/CQ/DQ pins at
time T
At time T
becomes valid-High, resetting the slice register. This is reflected on any of the
AQ/BQ/CQ/DQ pins at time T
Table
CKO
shows generic single-port, dual-port, and quad-port distributed RAM
CINCK
SRCK
RAM Size
after clock event 1.
128-bit
128-bit
256-bit
32-bit
32-bit
32-bit
64-bit
64-bit
64-bit
5-11.
before clock event 3, the SR signal (configured as synchronous reset)
before clock event 1, data from CIN input becomes valid-High at the
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CKO
after clock event 3.
Single-port
Single-port
Single-port
Single-port
Quad-port
Quad-port
Dual-port
Dual-port
Dual-port
Type
A[4:0] (read/write)
A[4:0] (read/write)
DPRA[4:0] (read)
ADDRA[4:0] (read)
ADDRB[4:0] (read)
ADDRC[4:0] (read)
ADDRD[4:0] (read/write)
A[5:0] (read/write)
A[5:0] (read/write)
DPRA[5:0] (read)
ADDRA[5:0] (read)
ADDRB[5:0] (read)
ADDRC[5:0] (read)
ADDRD[5:0] (read/write)
A[6:0] (read/write)
A[6:0], (read/write)
DPRA[6:0] (read)
A[7:0] (read/write)
Address Inputs
CLB Primitives
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