XC3S700AN-4FGG484C Xilinx Inc, XC3S700AN-4FGG484C Datasheet - Page 47

• Manufacturer Part Number: XC3S700AN-4FGG484C
• Description: IC SPARTAN-3AN FPGA 700K 484FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S700AN-4FGG484C

• Total Ram Bits: 368640
• Number Of Logic Elements/cells: 13248
• Number Of Labs/clbs: 1472
• Number Of I /o: 372
• Number Of Gates: 700000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-BBGA
• No. Of Logic Blocks: 13248
• No. Of Gates: 700000
• No. Of Macrocells: 13248
• Family Type: Spartan-3AN
• No. Of Speed Grades: 4
• No. Of I/o's: 372
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1528 - KIT STARTER SPARTAN-3 AN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1556

Configurable Logic Block (CLB) Timing
Table 33: CLB (SLICEM) Timing
DS557 (v4.1) April 1, 2011
Product Specification
Notes:
1.
Clock-to-Output Times
T
Setup Times
T
T
Hold Times
T
T
Clock Timing
T
T
F
Propagation Times
T
Set/Reset Pulse Width
T
AS
AH
CKO
DICK
CKDI
CH
CL
TOG
ILO
RPW_CLB
The numbers in this table are based on the operating conditions set forth in
Symbol
When reading from the FFX (FFY) Flip-Flop, the time
from the active transition at the CLK input to data
appearing at the XQ (YQ) output
Time from the setup of data at the F or G input to the
active transition at the CLK input of the CLB
Time from the setup of data at the BX or BY input to
the active transition at the CLK input of the CLB
Time from the active transition at the CLK input to the
point where data is last held at the F or G input
Time from the active transition at the CLK input to the
point where data is last held at the BX or BY input
The High pulse width of the CLB’s CLK signal
The Low pulse width of the CLK signal
Toggle frequency (for export control)
The time it takes for data to travel from the CLB’s F
(G) input to the X (Y) output
The minimum allowable pulse width, High or Low, to
the CLB’s SR input
Description
www.xilinx.com
Spartan-3AN FPGA Family: DC and Switching Characteristics
Table
0.63
0.18
1.58
0.63
1.33
Min
–
0
0
0
–
10.
-5
Max
0.60
0.62
770
Speed Grade
–
–
–
–
–
–
–
0.36
1.88
0.75
0.75
1.61
Min
–
0
0
0
–
-4
Max
0.68
0.71
667
–
–
–
–
–
–
–
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
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