XC3S700AN-4FGG484C Xilinx Inc, XC3S700AN-4FGG484C Datasheet - Page 29
![IC SPARTAN-3AN FPGA 700K 484FBGA](/photos/6/72/67299/pk081-484_sml.jpg)
XC3S700AN-4FGG484C
Manufacturer Part Number
XC3S700AN-4FGG484C
Description
IC SPARTAN-3AN FPGA 700K 484FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr
Datasheets
1.XC3S50A-4VQG100C.pdf
(7 pages)
2.XC3S50AN-4TQG144C.pdf
(2 pages)
3.XC3S50AN-4TQG144C.pdf
(123 pages)
Specifications of XC3S700AN-4FGG484C
Total Ram Bits
368640
Number Of Logic Elements/cells
13248
Number Of Labs/clbs
1472
Number Of I /o
372
Number Of Gates
700000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-BBGA
No. Of Logic Blocks
13248
No. Of Gates
700000
No. Of Macrocells
13248
Family Type
Spartan-3AN
No. Of Speed Grades
4
No. Of I/o's
372
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
122-1528 - KIT STARTER SPARTAN-3 AN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1556
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S700AN-4FGG484C
Manufacturer:
XilinxInc
Quantity:
3 000
Company:
Part Number:
XC3S700AN-4FGG484C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Table 23: Setup and Hold Times for the IOB Input Path (Cont’d)
Table 24: Sample Window (Source Synchronous)
DS557 (v4.1) April 1, 2011
Product Specification
Notes:
1.
2.
3.
T
Set/Reset Pulse Width
T
Symbol
T
IOICKPD
RPW_IOB
SAMP
Symbol
The numbers in this table are tested using the methodology presented in
Table 10
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the
appropriate Input adjustment from
These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract
the appropriate Input adjustment from
edge.
Setup and hold
capture window of
an IOB flip-flop.
and
Description
Time from the active transition at the
ICLK input of the Input Flip-Flop (IFF)
to the point where data must be held
at the Input pin. The Input Delay is
programmed.
Minimum pulse width to SR control
input on IOB
Table
13.
Description
The input capture sample window value is highly specific to a particular application, device,
package, I/O standard, I/O placement, DCM usage, and clock buffer. Please consult the
appropriate Xilinx Answer Record for application-specific values.
• Answer Record
Table
Table
26.
26. When the hold time is negative, it is possible to change the data before the clock’s active
30879
LVCMOS25
Conditions
www.xilinx.com
Spartan-3AN FPGA Family: DC and Switching Characteristics
–
(3)
Table 30
Maximum
DELAY_
VALUE
IFD_
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
–
and are based on the operating conditions set forth in
XC3S400AN
XC3S700AN
XC3S1400AN
All
Device
–1.12
–1.70
–2.08
–2.38
–2.23
–2.69
–3.08
–3.35
–1.67
–2.27
–2.59
–2.92
–2.89
–3.22
–3.52
–3.81
–1.60
–2.06
–2.46
–2.86
–2.88
–3.24
–3.55
–3.89
1.33
Min
Speed Grade
-5
–1.12
–1.70
–2.08
–2.38
–2.23
–2.69
–3.08
–3.35
–1.67
–2.27
–2.59
–2.92
–2.89
–3.22
–3.52
–3.81
–1.60
–2.06
–2.46
–2.86
–2.88
–3.24
–3.55
–3.89
1.61
Min
-4
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
29