EP2SGX60EF1152I4 Altera, EP2SGX60EF1152I4 Datasheet - Page 44

• Manufacturer Part Number: EP2SGX60EF1152I4
• Description: IC STRATIX II GX 60K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX60EF1152I4

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 534
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 60440
• # I/os (max): 534
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 60440
• Ram Bits: 2544192
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-2186

Transceivers
Figure 2–29. EP2SGX130 Device Inter-Transceiver and Global Clock Connections
Notes to
(1)
(2)
(3)
2–36
Stratix II GX Device Handbook, Volume 1
There are two transmitter PLLs in each transceiver block.
There are four receiver PLLs in each transceiver block.
The Global Clock line must be driven by an input pin.
Figure
2–29:
From Global
Clock Line (3)
16 Interface Clocks
To PLD
Global Clocks
IQ[4..0]
Global clk line
Global clk line
Global clk line
Global clk line
Global clk line
Global clk line
Global clk line
Global clk line
Global clk line
Global clk line
IQ[4..0]
IQ[4..0]
IQ[4..0]
IQ[4..0]
IQ[4..0]
To IQ0
IQ[4..0]
IQ[4..0]
To IQ1
IQ[4..0]
IQ[4..0]
To IQ4
IQ[4..0]
To IQ2
IQ[4..0]
IQ[4..0]
To IQ3
IQ[4..0]
IQ[4..0]
REFCLK0
REFCLK1
REFCLK0
REFCLK1
REFCLK0
REFCLK1
REFCLK0
REFCLK1
REFCLK0
REFCLK1
Transceiver Block 0
Transceiver Block 1
Transceiver Block 2
IQ[4..0]
Transceiver Block 3
Transceiver Block 4
÷2
÷2
÷2
÷2
÷2
÷2
÷2
÷2
÷2
÷2
From Global Clock Line (3)
From Global Clock Line (3)
From Global Clock Line (3)
From Global Clock Line (3)
From Global Clock Line (3)
Transceiver Clock Generator Block
Transceiver Clock Generator Block
Transceiver Clock Generator Block
Transceiver Clock Generator Block
Transceiver Clock Generator Block
Transmitter
Transmitter
Transmitter
Transmitter
Transmitter
PLL 1
PLL 1
PLL 1
PLL 1
PLL 1
Transmitter
Transmitter
PLL 0
Transmitter
PLL 0
Transmitter
Transmitter
PLL 0
PLL 0
PLL 0
Receiver
Receiver
Receiver
Receiver
Receiver
PLLs
PLLs
PLLs
PLLs
PLLs
4
4
4
4
4
Altera Corporation
October 2007