EP2SGX60EF1152I4 Altera, EP2SGX60EF1152I4 Datasheet - Page 36

• Manufacturer Part Number: EP2SGX60EF1152I4
• Description: IC STRATIX II GX 60K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX60EF1152I4

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 534
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 60440
• # I/os (max): 534
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 60440
• Ram Bits: 2544192
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-2186

Transceivers
Figure 2–23. 20-Bit to 16-Bit Decoding Process
2–28
Stratix II GX Device Handbook, Volume 1
CTRL[1..0]
MSB
19
j
1
h
18
1
15
H
1
17
g
1
G
14
1
16
f
1
13
F
1
15
i
1
13
E
asserted. All 8B/10B control signals, such as disparity error or control
detect, are pipelined with the data in the Stratix II GX receiver block and
are edge aligned with the data.
Figure 2–23
2-bit control indicator.
There are two optional error status ports available in the 8B/10B decoder,
rx_errdetect and rx_disperr. These status signals are aligned with
the code group in which the error occurred.
Receiver State Machine
The receiver state machine operates in Basic, GIGE, PCI Express, and
XAUI modes. In GIGE mode, the receiver state machine replaces invalid
code groups with K30.7. In XAUI mode, the receiver state machine
translates the XAUI PCS code group to the XAUI XGMII code group.
Byte Deserializer
The byte deserializer widens the transceiver data path before the FPGA
interface. This reduces the rate at which the received data needs to be
clocked at in the FPGA logic. The byte deserializer block is available in
both single- and double-width modes.
The byte deserializer converts the one- or two-byte interface into a
two- or four-byte-wide data path from the transceiver to the FPGA logic
(see
deserializer is needed to widen the bus width at the FPGA interface and
1
14
e
1
11
D
Table
1
13
d
1
10
C
Cascaded 8B/10B Conversion
1
2–9). The FPGA interface has a limit of 250 MHz, so the byte
c
12
1
shows how the 20-bit code is decoded to the 16-bit data +
B
9
1
b
11
1
A
8
1
10
a
1
H
7
9
j
G
6
h
8
5
F
g
7
E
4
6
3
D
f
5
2
C
i
1
B
e
4
0
A
d
3
Altera Corporation
Parallel Data
c
2
October 2007
b
1
LSB
a
0