EP2SGX60EF1152I4 Altera, EP2SGX60EF1152I4 Datasheet - Page 159

• Manufacturer Part Number: EP2SGX60EF1152I4
• Description: IC STRATIX II GX 60K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX60EF1152I4

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 534
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 60440
• # I/os (max): 534
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 60440
• Ram Bits: 2544192
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-2186

SignalTap II
Embedded Logic
Analyzer
Configuration
Altera Corporation
October 2007
EP2SGX30
EP2SGX60
EP2SGX90
EP2SGX130
Table 3–3. 32-Bit Stratix II GX Device IDCODE
Device
Version (4 Bits)
0000
0000
0000
0000
The Stratix II GX device instruction register length is 10 bits and the
USERCODE
scan register length and device IDCODE information for Stratix II GX
devices.
Stratix II GX devices feature the SignalTap II embedded logic analyzer,
which monitors design operation over a period of time through the IEEE
Std. 1149.1 (JTAG) circuitry. You can analyze internal logic at speed
without bringing internal signals to the I/O pins. This feature is
particularly important for advanced packages, such as FineLine BGA
packages, because it can be difficult to add a connection to a pin during
the debugging process after a board is designed and manufactured.
The logic, circuitry, and interconnects in the Stratix II GX architecture are
configured with CMOS SRAM elements. Altera
reconfigurable and every device is tested with a high coverage
production test program so you do not have to perform fault testing and
can instead focus on simulation and design verification.
Stratix II GX devices are configured at system power-up with data stored
in an Altera configuration device or provided by an external controller
(for example, a MAX
Stratix II GX devices using the fast passive parallel (FPP), active serial
Table 3–2. Stratix II GX Boundary-Scan Register Length
register length is 32 bits.
0010 0000 1110 0001
0010 0000 1110 0010
0010 0000 1110 0011
0010 0000 1110 0100
EP2SGX130
Part Number (16 Bits)
EP2SGX30
EP2SGX60
EP2SGX90
Device
®
II device or microprocessor). You can configure
IDCODE (32 Bits)
Stratix II GX Device Handbook, Volume 1
Tables 3–2
Manufacturer Identity
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
Boundary-Scan Register Length
(11 Bits)
and
®
3–3
FPGAs are
Configuration & Testing
1,320
1,506
2,016
2,454
show the boundary-
LSB (1 Bit)
1
1
1
1
3–3