ADSP-BF532SBST400 Analog Devices Inc, ADSP-BF532SBST400 Datasheet - Page 3

• Manufacturer Part Number: ADSP-BF532SBST400
• Description: IC DSP CTLR 16BIT 400MHZ 176LQFP
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF532SBST400

• Rohs Status: RoHS non-compliant
• Interface: SPI, SSP, UART
• Clock Rate: 400MHz
• Non-volatile Memory: ROM (1 kB)
• On-chip Ram: 84kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP
• Device Core Size: 16b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Mips: 400
• Device Input Clock Speed: 400MHz
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 1.2/1.8/2.5/3.3V
• Operating Supply Voltage (min): 0.8/1.75V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: LQFP
• For Use With: ADZS-BF533-EZLITE - KIT W/BOARD EVAL FOR ADSP-BF533
• Lead Free Status / Rohs Status: Not Compliant

Silicon Anomaly List
Key: x = anomaly exists in revision
No.
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
. = Not applicable
ID
05000258
05000260
05000261
05000262
05000263
05000264
05000265
05000269
05000270
05000271
05000272
05000273
05000276
05000277
05000278
05000281
05000282
05000283
05000288
05000301
05000302
05000305
05000306
05000310
05000311
05000312
05000313
05000315
05000319
05000357
05000363
05000366
05000371
05000400
05000402
05000403
05000416
Description
Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ
ICPLB_STATUS MMR Register May Be Corrupted
DCPLB_FAULT_ADDR MMR Register May Be Corrupted
Stores To Data Cache May Be Lost
Hardware Loop Corrupted When Taking an ICPLB Exception
CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop
Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks
High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase
High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease
Spontaneous Reset of Internal Voltage Regulator
Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V
Writes to Synchronous SDRAM Memory May Be Lost
Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero
PPI_DELAY
Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt
Disabling Peripherals with DMA Running May Cause DMA System Instability
False Hardware Error Exception when ISR Context Is Not Restored
Memory DMA Corruption with 32-Bit Data and Traffic Control
System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage
SPORTs May Receive Bad Data If FIFOs Fill Up
Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space
SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly
SPORT_HYS Bit in PLL_CTL Register Is Not Functional
ALT_TIMING Bit in PPI_CONTROL Register Is Not Functional
False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory
Erroneous Flag (GPIO) Pin Operations under Specific Sequences
Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted
PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes
Killed System MMR Write Completes Erroneously on Next System MMR Access
Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages
Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled
UART Break Signal Issues
PPI Underflow Error Goes Undetected in ITU-R 656 Mode
Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration
PPI Does Not Start Properly In Specific Mode
SSYNC Stalls Processor when Executed from Non-Cacheable Memory
Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall
Speculative Fetches Can Cause Undesired External FIFO Operations
NR003532D | Page 3 of 45 | July 2008
ADSP-BF531/BF532/BF533
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