ADSP-BF532SBST400 Analog Devices Inc, ADSP-BF532SBST400 Datasheet - Page 13

• Manufacturer Part Number: ADSP-BF532SBST400
• Description: IC DSP CTLR 16BIT 400MHZ 176LQFP
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF532SBST400

• Rohs Status: RoHS non-compliant
• Interface: SPI, SSP, UART
• Clock Rate: 400MHz
• Non-volatile Memory: ROM (1 kB)
• On-chip Ram: 84kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP
• Device Core Size: 16b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Mips: 400
• Device Input Clock Speed: 400MHz
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 1.2/1.8/2.5/3.3V
• Operating Supply Voltage (min): 0.8/1.75V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: LQFP
• For Use With: ADZS-BF533-EZLITE - KIT W/BOARD EVAL FOR ADSP-BF533
• Lead Free Status / Rohs Status: Not Compliant

Silicon Anomaly List
20.
21.
22.
DESCRIPTION:
The problem can occur when 3 or more consecutive DMA reads from a single L1 memory bank (Bank A or Bank B) are stalled for an
extended period of time (due to core or cache activity). In this situation, when a subsequent L1 DMA read is initiated from a different
bank, it is possible that the data from the last 2 reads will collide, corrupting the data.
WORKAROUND:
There are two workarounds for this issue:
1) Locate all DMA data within the same L1 memory bank (for example, bank A or bank B).
2) Ensure that only 1 DMA Channel reads from a given L1 memory bank at any given time.
APPLIES TO REVISION(S):
0.3
DESCRIPTION:
When Writethrough cache is enabled and DCPLB_DATAx:CPLB_L1_AOW = 0 (Allocate Cache Lines on Reads Only), incorrect data may be
read in the following scenario:
• Must write to an address which is writethrough cacheable in no-allocate-on-write mode, and cache miss must occur
• Must read above address while write is still in Store buffer (not yet in Write buffer or destination memory location)
• Must then read above address again after it drains from Store buffer. Data returned from cache will be incorrect but the destination
memory location will have correct value.
WORKAROUND:
When configuring data cache as writethrough, set DCPLB_DATAx:CPLB_L1_AOW = 1 (allocate cache lines on reads and writes) to avoid
the possibility of this anomaly.
APPLIES TO REVISION(S):
0.3
DESCRIPTION:
When a "brown-out" occurs, the internal Voltage regulator cannot be reset using the hardware reset pin. A "brown-out" is defined as a
condition in which VDDext drops below the range specified in the data sheet, but does not drop all the way to 0 V, before it returns to the
proper value.
WORKAROUND:
In order to recover from a "brown-out", the processor must be powered down completely and then powered back up.
APPLIES TO REVISION(S):
0.3
05000203 - Specific Sequence That Can Cause DMA Error or DMA Stopping:
05000204 - Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode:
05000207 - Recovery from "Brown-Out" Condition:
NR003532D | Page 13 of 45 | July 2008
ADSP-BF531/BF532/BF533