ADSP-BF532SBST400 Analog Devices Inc, ADSP-BF532SBST400 Datasheet

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... Silicon Anomaly List ABOUT ADSP-BF531/BF532/BF533 SILICON ANOMALIES These anomalies represent the currently known differences between revisions of the Blackfin ADSP-BF531/BF532/BF533 product(s) and the functionality specified in the ADSP-BF531/BF532/BF533 data sheet(s) and the Hardware Reference book(s). SILICON REVISIONS A silicon revision number with the form "-x.x" is branded on all parts. The implementation field bits <15:0> of the DSPID core MMR register can be used to differentiate the revisions as shown below ...

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... ADSP-BF531/BF532/BF533 SUMMARY OF SILICON ANOMALIES The following table provides a summary of ADSP-BF531/BF532/BF533 anomalies and the applicable silicon revision(s) for each anomaly. No. ID Description 1 05000074 Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported 2 05000099 UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time ...

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... SSYNC Stalls Processor when Executed from Non-Cacheable Memory 78 05000403 Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall 79 05000416 Speculative Fetches Can Cause Undesired External FIFO Operations Key anomaly exists in revision . = Not applicable ADSP-BF531/BF532/BF533 NR003532D | Page July 2008 0.3 0.4 0.5 0 ...

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... ADSP-BF531/BF532/BF533 DETAILED LIST OF SILICON ANOMALIES The following list details all known silicon anomalies for the ADSP-BF531/BF532/BF533 including a description, workaround, and identification of applicable silicon revisions. 1. 05000074 - Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported: DESCRIPTION: A multi-issue instruction with dsp32shiftimm in slot 1 and a P register store in slot 2 is not supported. It will cause an exception. ...

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... PEN | WLS(8) (z); w[p0+UART_LCR-UART_GCTL ERBFI | ELSI (z); w[p0+UART_IER-UART_GCTL] = r1; receive_polling w[p2] (z bittst (r2, bitpos (IRQ_UART_RX)); if !CC jump receive_polling; data_ready: csync w[p0+UART_LSR-UART_GCTL] (z w[p0+UART_RBR-UART_GCTL] (z bittst (r2, bitpos (IRQ_UART_ERROR)); if CC jump error_handler; [i0++] = r0; jump receive_polling; APPLIES TO REVISION(S): 0.3, 0.4 ADSP-BF531/BF532/BF533 NR003532D | Page July 2008 ...

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... ADSP-BF531/BF532/BF533 3. 05000105 - Watchpoint Status Register (WPSTAT) Bits Are Set on Every Corresponding Match: DESCRIPTION: Even when the Watchpoint Data Address Counters (WPDACTL:WPDCNTENx) are enabled, the corresponding Watchpoint Status Register bits (WPSTAT:STATDAx) will be set on every match, not just on the expiration of the counter. The same is true for the Watchpoint Instruction Address Counters (WPIACTL:WPICNTENx) and Status Bits (WPSTAT:STATIAx). ...

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... If the processor is either not DMAing to instruction memory or not using data cache, you will not encounter this problem. The VisualDSP++ runtime libraries cache support functions contain a workaround for this anomaly where necessary. APPLIES TO REVISION(S): 0.3, 0.4 ADSP-BF531/BF532/BF533 // Check System Reset Configuration Register // Check NO BOOT ON SOFTWARE RESET Bit // Set NO BOOT ON SOFTWARE RESET Bit ...

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... ADSP-BF531/BF532/BF533 7. 05000166 - PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits: DESCRIPTION: For PPI data lengths greater than 8 and less than 16, the upper bits received into memory that are not part of the PPI data should be zero. For example, if the user is using 10-bit PPI data length, the upper 6 bits in memory should be zero. Instead, the PPI captures whatever data is on the upper 6 PPI data pins (muxed as PFx pins) ...

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... The default VisualDSP++ LDFs include a workaround for this hardware anomaly. The workaround will be automatically enabled for the appropriate silicon revisions, or the workaround can be enabled manually by defining the macro __WORKAROUND_AVOID_LDF_BLOCK_BOUNDARIES when linking. When enabled, the LDFs will reserve 76 bytes at the boundaries of valid memory blocks. APPLIES TO REVISION(S): 0.3 ADSP-BF531/BF532/BF533 NR003532D | Page July 2008 ...

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... ADSP-BF531/BF532/BF533 13. 05000193 - False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed: DESCRIPTION: Consider the following scenario: 1) Pins are configured as edge-sensitive inputs. 2) The interrupt occurs on the rising edge. 3) Input level is constant and 0. 4) Change the polarity setting to set the interrupt to occur on the falling edge instead. ...

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... The carry fix cycle occurs when the DMA address is being modified such that the address crosses a 64k boundary. If the DMA address cannot cross a 64k address boundary, the read will never be incorrect. WORKAROUND: 1) Avoid DMA addresses that cross a 64K address boundary Read the DMA Current Address register twice to verify value read. APPLIES TO REVISION(S): 0.3 ADSP-BF531/BF532/BF533 NR003532D | Page July 2008 ...

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... ADSP-BF531/BF532/BF533 17. 05000200 - SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions: DESCRIPTION: In multichannel mode, the SPORT's MRCS registers are used to select which channels are active (transmitted or received) and which ones are to be ignored. For each ignored channel, the DT output will be three-stated. The problem is seen when "Multichannel DMA packing" ...

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... VDDext drops below the range specified in the data sheet, but does not drop all the way before it returns to the proper value. WORKAROUND: In order to recover from a "brown-out", the processor must be powered down completely and then powered back up. APPLIES TO REVISION(S): 0.3 ADSP-BF531/BF532/BF533 NR003532D | Page July 2008 ...

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... ADSP-BF531/BF532/BF533 23. 05000208 - VSTAT Status Bit in PLL_STAT Register Is Not Functional: DESCRIPTION: The VSTAT status bit in the PLL_STAT register does not function. Relying on its value to determine whether the internal voltage regulator has settled is not recommended. WORKAROUND: When changing the voltage via the internal voltage regulator, allow at least 40usec for the voltage change to take place. After 40usec, the new value will be set, regardless of the state of the VSTAT bit ...

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... For Clock Divisor values greater than 1 (as determined by the UART_DLL and UART_DLH registers), the pulse width can assume values of 14/16th or 15/16th of the nominal bit time. Data, Parity and Stop bits have proper duration. The data will be correctly received. See anomalies 05000230 and 05000231 regarding UART timing. WORKAROUND: None APPLIES TO REVISION(S): 0.3, 0.4 ADSP-BF531/BF532/BF533 NR003532D | Page July 2008 ...

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... ADSP-BF531/BF532/BF533 28. 05000227 - Scratchpad Memory Bank Reads May Return Incorrect Data: DESCRIPTION: Reads from the scratchpad memory may return incorrect data under some conditions. The problem occurs when reads of scratchpad memory are immediately followed by another read (of any location, including non-scratchpad locations), where the addresses being accessed do not have the same least significant address bit ...

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... However, the receiver will sample and test the number of stop-bits set by the STB bit. This incorrect behavior also affects framing error detection. Note that this anomaly makes the workaround for anomaly 05000230 not applicable to the case of a bidirectional link composed of two Blackfin devices. WORKAROUND: None APPLIES TO REVISION(S): 0.3, 0.4 ADSP-BF531/BF532/BF533 NR003532D | Page July 2008 ...

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... ADSP-BF531/BF532/BF533 32. 05000233 - PPI_FS3 Is Not Driven Internal Frame Sync Transmit Modes: DESCRIPTION: In this mode, if the PORT_CFG field in the PPI_CONTROL register is set to #b11 (Sync PPI_FS3 to PPI_FS2), the PPI_FS3 frame sync signal is not driven to the PF3 flag pin. It is, however, correctly driven to PF3 when the PORT_CFG field is set to #b01 (Sync PPI_FS3 to PPI_FS1). ...

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... For exceptions, 3 padding NOPs should be implemented following any access to a cacheable region of memory. Finally, as the workaround involves Supervisor Mode instructions to disable and enable interrupts, this does not apply to User Mode. In user space, do not use CSYNC or SSYNC instructions. ADSP-BF531/BF532/BF533 IF CC JUMP X (BP); ... ...

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... ADSP-BF531/BF532/BF533 APPLIES TO REVISION(S): 0.3, 0.4 36. 05000245 - Spurious Hardware Error from an Access in the Shadow of a Conditional Branch: DESCRIPTION: The anomaly is only an issue if there is a load which may access reserved or illegal memory on the opposite control flow of a conditional jump to the taken path. The following sequences demonstrate how this anomaly can appear: Sequence #1: For the " ...

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... The specification in the data sheet and hardware reference manual allows for TMRCLK and TACLK speeds 1/2 SCLK. However, the maximum rate is less than this limit. The minimum SCLK/TMRCLK or SCLK/TACLK ratio is somewhere in the range of 2.5 to 2.7. The exact value is not yet characterized. WORKAROUND: A minimum SCLK/TMRCLK or SCLK/TACLK ratio safe to use. APPLIES TO REVISION(S): 0.3, 0.4 ADSP-BF531/BF532/BF533 NR003532D | Page July 2008 ...

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... ADSP-BF531/BF532/BF533 40. 05000254 - Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock: DESCRIPTION Timer is in PWM_OUT mode AND is clocked by an external clock as opposed to the system clock (i.e., clocked by a signal applied to either PPI_CLK or a flag pin) AND is in single-pulse mode (PERIOD_CNT = 0), then the generated pulse width may be off count. ...

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... The compiler would normally only save these registers if they were used within the handler routine. The macro __WORKAROUND_SHORT_LOOP_EXCEPTIONS will be defined at compile, assemble and link build phases when the workaround is enabled. APPLIES TO REVISION(S): 0.3, 0.4 ADSP-BF531/BF532/BF533 NR003532D | Page July 2008 ...

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... ADSP-BF531/BF532/BF533 43. 05000258 - Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ: DESCRIPTION: When bit 9 and bit 12 of the ICPLB Data MMR differ, the cache may not update properly. For example, for a particular cache line, the cache tag may be valid while the contents of that cache line are not present in the cache. ...

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... The VisualDSP++ Blackfin Runtime Libraries include a workaround for this anomaly. The workaround ignores DCPLB miss exceptions the first time they are raised from a particular PC. The fault address is guaranteed to be correct the second time. APPLIES TO REVISION(S): 0.3, 0.4 ADSP-BF531/BF532/BF533 NR003532D | Page July 2008 ...

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... ADSP-BF531/BF532/BF533 46. 05000262 - Stores To Data Cache May Be Lost: DESCRIPTION: A committed pending write into the sub-bank targeted by the first of two consecutive dual-DAG operations will be lost when: 1) Data cache is enabled, AND 2) For the first dual-DAG access, DAG0 is a cache miss, DAG1 is a read, and both accesses alias to the same non-L1 sub-bank, AND 3) The second dual-DAG is the next instruction, and DAG1 is an access (read or write SRAM, AND 4) There's an unpredicted change of flow within three clock cycles after the first dual-DAG access ...

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... With the workaround enabled, the compiler will ensure that the second to last instruction of a hardware loop is not a CSYNC, SSYNC or IDLE instruction, which has the potential to trigger the anomaly. The macro __WORKAROUND_PRE_LOOP_END_SYNC_STALL_264 will be defined at compile, assemble, and link build phases when the workaround is enabled. APPLIES TO REVISION(S): 0.3, 0.4 ADSP-BF531/BF532/BF533 NR003532D | Page July 2008 ...

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... ADSP-BF531/BF532/BF533 49. 05000265 - Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks: DESCRIPTION: A noisy board environment combined with slow input edge rates on external SPORT receive (RSCLK) and transmit clocks (TSCLK) may cause a variety of observable problems. Spurious high frequency transitions on the RSCLK/TSCLK can cause the SPORT to recognize an extra noise-induced glitch clock pulse ...

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... Reduce the I/O activity if possible (for example, operate at a lower SCLK frequency rate). • Follow the requirements in application note EE-228. In addition, use a PMOS FET with the lowest gate charge ratings consistent with your application's current rating needs. APPLIES TO REVISION(S): 0.3, 0.4 ADSP-BF531/BF532/BF533 NR003532D | Page July 2008 ...

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... ADSP-BF531/BF532/BF533 51. 05000270 - High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease: DESCRIPTION: Heavy I/O activity can cause VDDint to decrease. The reference voltage, which is used to create the set point for the loop, is decreased by the supply noise. The voltage may drop to a level that is lower than the minimum required to meet your application's frequency of operations ...

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... When the PPI_DELAY register is a non-zero value, the frame sync setup time increases by one half the period of the PPI clock. The delay starts counting at the point on the existing diagrams where data is shown to be sampled. APPLIES TO REVISION(S): 0.3, 0.4, 0.5, 0.6 ADSP-BF531/BF532/BF533 NR003532D | Page July 2008 ...

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... ADSP-BF531/BF532/BF533 56. 05000277 - Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt: DESCRIPTION write to any I/O data register (data, clear, set and toggle registers) occurs one system clock cycle after an edge is detected on an edge- triggered interrupt, then the bit may be cleared one system clock cycle after it has been set. ...

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... This anomaly is avoided if MDMA channels are used in 16-bit mode or if traffic control is disabled (DMA_TC_PER = 0x0000). Note: on this device, the 16-bit MDMA is more efficient than the 32-bit mode for transfers from L1 to external memory and vice versa. APPLIES TO REVISION(S): 0.3, 0.4, 0.5 ADSP-BF531/BF532/BF533 NR003532D | Page July 2008 ...

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... ADSP-BF531/BF532/BF533 60. 05000283 - System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage: DESCRIPTION: Consider the following sequence: 1) System MMR write is stalled. 2) Interrupt occurs while the System MMR write is stalled (thus killing the write). 3) Interrupt Service Routine performs an "ssync;" instruction. In order for this anomaly to happen, the interrupt must kill the write in one particular stage of the execution pipeline. In this case, the anomaly will cause the MMR logic to think that the killed System MMR access is still valid. The " ...

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... DMA may not appear to fail until the next descriptor fetch, when it fetches an invalid pointer. WORKAROUND: Place source and destination descriptors in the same memory space. Both should be located either in external or internal memory. APPLIES TO REVISION(S): 0.3, 0.4, 0.5 ADSP-BF531/BF532/BF533 NR003532D | Page July 2008 ...

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... ADSP-BF531/BF532/BF533 63. 05000302 - SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly: DESCRIPTION: When a DMA channel has been granted permission to fetch descriptors from memory, writes to System MMRs associated with the same DMA controller will be held off until the descriptor fetch completes, regardless of the presence of an SSYNC instruction. ...

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... Have the exception handler confirm whether the exception was valid or not before taking action. This can be done by verifying if the CODE_FAULT_ADDR (or the DATA_FAULT_ADDR) register contains an address that is within a valid page. In that case, no action is performed. Note that this anomaly also happens on the boundary of L1_code_cache if instruction cache is enabled. APPLIES TO REVISION(S): 0.3, 0.4, 0.5, 0.6 ADSP-BF531/BF532/BF533 NR003532D | Page July 2008 ...

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... ADSP-BF531/BF532/BF533 67. 05000311 - Erroneous Flag (GPIO) Pin Operations under Specific Sequences: DESCRIPTION: When an access to a GPIO / Flag IO System MMR (any register with a PORTFIO_ or FIO_ prefix) is followed by another System MMR access that is not in the GPIO / Flag IO block, the GPIO's input driver can spuriously become active for a moment result, the output values held in the Port F latch may clear erroneously, causing unwanted transitions in pin state on the output pins ...

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... CSYNC or SSYNC instructions. Also, do not load the loop registers directly. Instead, utilize hardware loops which can be implemented with the LSETUP instruction, which limits loop ranges to 2046 bytes. APPLIES TO REVISION(S): 0.3, 0.4, 0.5 ADSP-BF531/BF532/BF533 NR003532D | Page July 2008 ...

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... ADSP-BF531/BF532/BF533 69. 05000313 - PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes: DESCRIPTION: When the PPI is configured to trigger on a single external frame sync, all of the transfers require an edge on the frame sync except for the first transfer. For the first transfer only, the frame sync input is level-sensitive. This will make the PPI begin a transfer if the frame sync is at the active state, which can cause the PPI to start prematurely ...

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... WORKAROUND: There are several possible workarounds to this: 1) Disable Multichannel Mode 2) Use Internal Receive Frame Syncs 3) Use a Multichannel Frame Delay > Use a Window Offset > Enable DMA Transmit Packing 6) Do not disable Channel 0 APPLIES TO REVISION(S): 0.3, 0.4, 0.5 ADSP-BF531/BF532/BF533 NR003532D | Page July 2008 ...

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... ADSP-BF531/BF532/BF533 73. 05000363 - UART Break Signal Issues: DESCRIPTION: When a Break signal is received, the UART controller should issue a single error interrupt. However, the controller issues a number of error interrupts instead generates an error interrupt for every bit time that the break signal is active. For example break signal holds the line low for ~250ms at a baud rate of 57600 ...

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... These workarounds are enabled automatically in VisualDSP++ when building for affected processors. The compiler workaround can be enabled manually using the -workaround avoid-quick-rts-371 switch. The assembler warning is controlled using the -anomaly-detect 05000371 switch. When the workarounds are enabled, the macro __WORKAROUND_AVOID_QUICK_RTS_371 is defined at compile, assemble and link stages. APPLIES TO REVISION(S): 0.3, 0.4, 0.5 ADSP-BF531/BF532/BF533 NR003532D | Page July 2008 ...

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... ADSP-BF531/BF532/BF533 76. 05000400 - PPI Does Not Start Properly In Specific Mode: DESCRIPTION: When the PPI port is configured in transmit mode with two internal frame syncs, the PPI will not start properly if the PPI Frame Sync 3 (PPI_FS3) pin is left floating. WORKAROUND: The PPI_FS3 pin must be pulled down when the PPI is configured in transmit mode with 2 internal frame syncs. ...

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... Reads performed using a DMA transfer do not need to be protected from speculative accesses. APPLIES TO REVISION(S): 0.3, 0.4, 0.5, 0.6 ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ADSP-BF531/BF532/BF533 /* Disable Interrupts */ /* Read from a FIFO Device /* Write that Generates a Data CPLB Page Miss */ /* Enable Interrupts */ ...