ADSP-BF532SBST400 Analog Devices Inc, ADSP-BF532SBST400 Datasheet - Page 24

• Manufacturer Part Number: ADSP-BF532SBST400
• Description: IC DSP CTLR 16BIT 400MHZ 176LQFP
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF532SBST400

• Rohs Status: RoHS non-compliant
• Interface: SPI, SSP, UART
• Clock Rate: 400MHz
• Non-volatile Memory: ROM (1 kB)
• On-chip Ram: 84kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP
• Device Core Size: 16b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Mips: 400
• Device Input Clock Speed: 400MHz
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 1.2/1.8/2.5/3.3V
• Operating Supply Voltage (min): 0.8/1.75V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: LQFP
• For Use With: ADZS-BF533-EZLITE - KIT W/BOARD EVAL FOR ADSP-BF533
• Lead Free Status / Rohs Status: Not Compliant

ADSP-BF531/BF532/BF533
43.
44.
DESCRIPTION:
When bit 9 and bit 12 of the ICPLB Data MMR differ, the cache may not update properly. For example, for a particular cache line, the cache
tag may be valid while the contents of that cache line are not present in the cache.
WORKAROUND:
Set bit 9 to the state of bit 12 in each ICPLB entry.
The VisualDSP++ Blackfin Runtime Libraries include a workaround for this anomaly.
The _cplb_mgr and _cplb_init routines (which are part of the default cache support in the runtime libraries) set bit 9 (reserved) to the
same state as bit 12 (CPLB_L1_CHBL).
APPLIES TO REVISION(S):
0.3, 0.4
DESCRIPTION:
The ICPLB Status register cannot be relied upon to determine which CPLB caused an exception. This register is corrupted if:
1) There is a jump to anywhere within the last 64 bits of a page (as defined by an ICPLB), AND
2) An instruction located within these last 64 bits generates an instruction exception, AND
3) Speculative instruction fetches increment into the next page and encounter another instruction exception cause.
When all of these criteria are met, ICPLB_STATUS will reflect the speculative instruction fetch rather than the initial exception cause.
WORKAROUND:
Handle instruction protection violations and ICPLB multiple hits without using this register.
Use the ICPLB_FAULT_ADDR register to see the address that caused the exception:
iterate through all the CPLB entries to see which of the CPLBs cover the fault address.
APPLIES TO REVISION(S):
0.3, 0.4
05000258 - Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ:
05000260 - ICPLB_STATUS MMR Register May Be Corrupted:
1) For CPLB misses, exceptions simply swap in a CPLB entry that covers the address in question.
2) For the case of multiple CPLB hits, use the ICPLB_FAULT_ADDR register to find out which address caused the exception and then
3) For a protection violation exception, the handling is user-specific.
NR003532D | Page 24 of 45 | July 2008
Silicon Anomaly List