ADSP-BF532SBST400 Analog Devices Inc, ADSP-BF532SBST400 Datasheet - Page 2

• Manufacturer Part Number: ADSP-BF532SBST400
• Description: IC DSP CTLR 16BIT 400MHZ 176LQFP
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF532SBST400

• Rohs Status: RoHS non-compliant
• Interface: SPI, SSP, UART
• Clock Rate: 400MHz
• Non-volatile Memory: ROM (1 kB)
• On-chip Ram: 84kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP
• Device Core Size: 16b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Mips: 400
• Device Input Clock Speed: 400MHz
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 1.2/1.8/2.5/3.3V
• Operating Supply Voltage (min): 0.8/1.75V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: LQFP
• For Use With: ADZS-BF533-EZLITE - KIT W/BOARD EVAL FOR ADSP-BF533
• Lead Free Status / Rohs Status: Not Compliant

ADSP-BF531/BF532/BF533
SUMMARY OF SILICON ANOMALIES
The following table provides a summary of ADSP-BF531/BF532/BF533 anomalies and the applicable silicon revision(s) for each anomaly.
No.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
1
2
3
4
5
6
7
8
9
ID
05000074
05000099
05000105
05000119
05000122
05000158
05000166
05000167
05000179
05000180
05000183
05000189
05000193
05000194
05000198
05000199
05000200
05000201
05000202
05000203
05000204
05000207
05000208
05000209
05000215
05000219
05000225
05000227
05000229
05000230
05000231
05000233
05000234
05000242
05000244
05000245
05000246
05000250
05000253
05000254
05000255
05000257
Description
Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported
UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time
Watchpoint Status Register (WPSTAT) Bits Are Set on Every Corresponding Match
DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops
Rx.H Cannot Be Used to Access 16-bit System MMR Registers
Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications)
PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits
Turning SPORTs on while External Frame Sync Is Active May Corrupt Data
PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes
PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs
Timer Pin Limitations for PPI TX Modes with External Frame Syncs
False Protection Exceptions when Speculative Fetch Is Cancelled
False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed
Restarting SPORT in Specific Modes May Cause Data Corruption
Failing MMR Accesses when Preceding Memory Read Stalls
Current DMA Address Shows Wrong Value During Carry Fix
SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions
Receive Frame Sync Not Ignored During Active Frames in SPORT Multi-Channel Mode
Possible Infinite Stall with Specific Dual-DAG Situation
Specific Sequence That Can Cause DMA Error or DMA Stopping
Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode
Recovery from "Brown-Out" Condition
VSTAT Status Bit in PLL_STAT Register Is Not Functional
Speed Path in Computational Unit Affects Certain Instructions
UART TX Interrupt Masked Erroneously
NMI Event at Boot Time Results in Unpredictable State
Incorrect Pulse-Width of UART Start Bit
Scratchpad Memory Bank Reads May Return Incorrect Data
SPI Slave Boot Mode Modifies Registers from Reset Value
UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions
UART STB Bit Incorrectly Affects Receiver Setting
PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes
Incorrect Revision Number in DSPID Register
DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset
If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures
Spurious Hardware Error from an Access in the Shadow of a Conditional Branch
Data CPLBs Should Prevent Spurious Hardware Errors
Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions
Maximum External Clock Speed for Timers
Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock
Entering Hibernate State with RTC Seconds Interrupt Not Functional
Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches
NR003532D | Page 2 of 45 | July 2008
Silicon Anomaly List
0.3
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
.
.
.
0.4
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
.
.
.
.
.
.
.
.
.
.
.
0.5
x
x
x
x
x
x
x
x
x
x
x
x
x
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
0.6
x
x
x
x
x
x
x
x
x
x
x
x
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.