AD14060BF-4 Analog Devices Inc, AD14060BF-4 Datasheet - Page 44

• Manufacturer Part Number: AD14060BF-4
• Description: IC DSP CMOS 32BIT 308CQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of AD14060BF-4

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 2MB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 308-CQFP
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Clock Freq (max): 40MHz
• Mips: 40
• Device Input Clock Speed: 40MHz
• Ram Size: 1.9073535156MB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 308
• Package Type: CQFP
• Lead Free Status / Rohs Status: Not Compliant

AD14060/AD14060L
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
50 pF on all pins (see Figure 31). The delay and hold specifica-
tions given should be derated by a factor of 1.5 ns/50 pF for
loads other than the nominal value of 50 pF. Figure 33 and
Figure 34 show how output rise time varies with capacitance.
Figure 35 graphically shows how output delays and holds vary
with load capacitance. (Note that this graph or derating does
not apply to output disable delays; see the Output Disable Time
section.) The graphs in Figure 33, Figure 34, and Figure 35
might not be linear outside the ranges shown.
INPUT OR
16.0
14.0
12.0
10.0
OUTPUT
8.0
6.0
4.0
3.7
2.0
1.1
Figure 31. Equivalent Device Loading for AC Measurement
Figure 32. Voltage Reference Levels for AC Measurements
0
0
Figure 33. Typical Output Rise Time (10% to 90% V
TO OUTPUT
20
1.5V
PIN
(except Output Enable/Disable)
40
vs. Load Capacitance (V
50pF
(Includes All Fixtures)
60
LOAD CAPACITANCE (pF)
80
RISE TIME
I
I
OL
OH
100
120
DD
FALL TIME
= 5 V)
140
1.5V
1.5V
160
DD
180
)
200
14.7
7.4
Rev. B | Page 44 of 48
NOMINAL
–0.7
–1.0
5.0
4.0
3.0
2.0
1.0
Figure 35. Typical Output Delay or Hold vs. Load Capacitance
3.5
3.0
2.5
2.0
1.5
1.0
0.6
0.5
18
16
14
12
10
0
8
6
4
2
0
25
0
0
Figure 36. Typical Output Rise Time (10% to 90% V
Figure 34. Typical Output Rise Time (0.8 V to 2.0 V)
20
20
at Maximum Case Temperature (V
50
vs. Load Capacitance (V
40
40
vs. Load Capacitance (V
RISE TIME
75
60
LOAD CAPACITANCE (pF)
60
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
Y = 0.0796X + 1.17
RISE TIME
FALL TIME
80
80
100
FALL TIME
100
100
125
120
120
DD
DD
= 3.3 V)
= 5 V)
140
140
150
DD
Y = 0.0467X + 0.55
= 5 V)
160
160
175
180
180
DD
)
200
200
200
4.5
2.9
1.6