AD14060BF-4 Analog Devices Inc, AD14060BF-4 Datasheet - Page 38

• Manufacturer Part Number: AD14060BF-4
• Description: IC DSP CMOS 32BIT 308CQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of AD14060BF-4

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 2MB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 308-CQFP
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Clock Freq (max): 40MHz
• Mips: 40
• Device Input Clock Speed: 40MHz
• Ram Size: 1.9073535156MB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 308
• Package Type: CQFP
• Lead Free Status / Rohs Status: Not Compliant

AD14060/AD14060L
LINK PORT I/O
Each individual SHARC features six 4-bit link ports that
facilitate SHARC-to-SHARC communication and external I/O
interfacing. Each link port can be configured for either 1× or 2×
operation, allowing each to transfer either four or eight bits
per cycle.
The link ports can operate independently and simultaneously,
with a maximum bandwidth of 40 MBytes/s each, or a total of
240 MBytes/s per SHARC.
The AD14060/AD14060L optimizes the link port connections
internally, and brings a total of 12 of the link ports off-module
for user-defined system connections. Internally, each SHARC
has a connection to the other three SHARCs with a dedicated
link port interface. Thus, each SHARC can directly interface
with its nearest and next-nearest neighbor. The remaining three
link ports from each SHARC are brought out independently
from each SHARC. A maximum of 480 MBytes/s link port
bandwidth is then available off of the AD14060/AD14060L.
The link port connections are shown in Figure 25.
Link Port 4, the boot-link port, is brought off independently
from each SHARC. Individual booting is then allowed, or
chained link-port booting is possible, as described in the
Multiprocessor Link-Port Booting section.
Link port data is packed into 32-bit or 48-bit words, and can be
directly read by the SHARC core processor or DMA transferred
to on-SHARC memory.
Each link port has its own double-buffered input and output
registers. Clock/acknowledge handshaking controls link port
transfers. Transfers are programmable as either transmit or
receive.
1
3
4
1
3
4
SHARC_A
SHARC_D
Figure 25. Link Port Connections
0
0
5
5
2 2
2 2
5
5
SHARC_B
SHARC_C
0
0
1
3
4
1
3
4
Rev. B | Page 38 of 48
SERIAL PORTS
The SHARC serial ports provide an inexpensive interface to a
wide variety of digital and mixed-signal peripheral devices.
Each SHARC has two serial ports. The AD14060/AD14060L
provides direct access to Serial Port 1 of each SHARC. Serial
Port 0 is bused in common to each SHARC, and brought off-
module.
The serial ports can operate at the full clock rate of the module,
providing each with a maximum data rate of 40 Mbit/s.
Independent transmit and receive functions provide more
flexible communications. Serial port data can be automatically
transferred to and from on-SHARC memory via DMA, and
each of the serial ports offers time-division-multiplexed (TDM)
multichannel mode.
The serial ports can operate with little-endian or big-endian
transmission formats, with word lengths selectable from 3 bits
to 32 bits. They offer selectable synchronization and transmit
modes as well as optional µ-law or A-law companding. Serial
port clocks and frame syncs can be internally or externally
generated.
PROGRAM BOOTING
The AD14060/AD14060L supports automatic downloading of
programs following power-up or a software reset. The SHARC
offers the following options for program booting:
•
•
•
•
In no-boot mode, the SHARC starts executing instructions
from Address 0x0040 0004 in external memory. The boot mode
is selected by the state of the following signals: BMS , EBOOT,
and LBOOT.
On the AD14060/AD14060L, SHARC_A’s boot mode is sepa-
rately controlled, while SHARC_B, C, and D are controlled as a
group. With this flexibility, the AD14060/AD14060L can be
configured to boot using any of the following methods.
Multiprocessor Host Booting
To boot multiple ADSP-21060 processors from a host, each
ADSP-21060 must have its EBOOT, LBOOT, and BMS pins
configured for host booting: EBOOT = 0, LBOOT = 0, and
BMS = 1. After system power-up, each ADSP-21060 is in the
idle state and the BR x bus request lines are de-asserted. The
host must assert the HBR input and boot each ADSP-21060 by
asserting its CS pin and downloading instructions.
From an 8-bit EPROM
From a host processor
Through the link ports
No boot