AD14060BF-4 Analog Devices Inc, AD14060BF-4 Datasheet - Page 35

• Manufacturer Part Number: AD14060BF-4
• Description: IC DSP CMOS 32BIT 308CQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of AD14060BF-4

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 2MB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 308-CQFP
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Clock Freq (max): 40MHz
• Mips: 40
• Device Input Clock Speed: 40MHz
• Ram Size: 1.9073535156MB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 308
• Package Type: CQFP
• Lead Free Status / Rohs Status: Not Compliant

MULTIPLIER
8 x 4 x 32
DAG1
CONNECT
BUS
(PX)
8 x 4 x 24
DAG2
CORE PROCESSOR
16 x 40-BIT
REGISTER
DATA
FILE
PM ADDRESS BUS
DM ADDRESS BUS
1× CLOCK
PM DATA BUS
DM DATA BUS
TIMER
BARREL
SHIFTER
SEQUENCER
PROGRAM
INSTRUCTION
32 x 48-BIT
CACHE
Figure 21. ADSP-21060 Processor Block Diagram (Core of AD10460)
40/32
CLKIN
RESET
RPBA
CPA
BOOTSELECT A
BOOTSELECT BCD
DMAR1, 2
DMAG1, 2
SPORT0
FLAG1
JTAG
Figure 22. Complete Shared Memory Multiprocessing System
24
32
48
ALU
SHARC_A
LINKS 1, 3, AND 4;
IRQ
FLAGS 2 AND 0;
TIMEXP,
SPORT1
SHARC_D
LINKS 1, 3, AND 4;
IRQ
FLAGS 2 AND 0;
TIMEXP,
SPORT1
(QUAD PROCESSOR CLUSTER)
2–0
2–0
AD14060/AD14060L
;
;
Rev. B | Page 35 of 48
PROCESSOR PORT
ADDR
ADDR
SHARC_B
LINKS 1, 3, AND 4;
IRQ
FLAGS 2 AND 0;
TIMEXP,
SPORT1
SHARC_C
LINKS 1, 3, AND 4;
IRQ
FLAGS 2 AND 0;
TIMEXP,
SPORT1
DUAL-PORTED BLOCKS
DUAL-PORTED SRAM
TWO INDEPENDENT
DATA
2–0
2–0
(MEMORY MAPPED)
;
;
DATA BUFFERS
STATUS, AND
REGISTERS
CONTROL,
DATA
IOP
DATA
IOD
48
I/O PROCESSOR
ADDR
DATA
ADRCLK
I/O PORT
PAGE
BR
REDY
DATA
MS
SBTS
ACK
HBR
HBG
31–0
47–0
WR
SW
RD
CS
1–6
3-0
SYSTEM EXPANSION
ADDR
IOA
SERIAL PORTS
17
CONTROLLER
LINK PORTS
ADDR
DMA
(2)
(6)
MULTIPROCESSOR
AD14060/AD14060L
EXTERNAL
HOST PORT
INTERFACE
ADDR BUS
DATA BUS
PORT
36
4
6
6
MUX
MUX
EMULATION
TEST AND
JTAG
32
48
7