AD14060BF-4 Analog Devices Inc, AD14060BF-4 Datasheet - Page 24

• Manufacturer Part Number: AD14060BF-4
• Description: IC DSP CMOS 32BIT 308CQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of AD14060BF-4

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 2MB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 308-CQFP
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Clock Freq (max): 40MHz
• Mips: 40
• Device Input Clock Speed: 40MHz
• Ram Size: 1.9073535156MB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 308
• Package Type: CQFP
• Lead Free Status / Rohs Status: Not Compliant

AD14060/AD14060L
Parameter
External Late Frame Sync
Switching Characteristics:
t
t
To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame
sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width.
1
2
3
4
DDTLFSE
DDTENFS
Referenced to sample edge.
RFS hold after RCK when MCE = 1, MFD = 0 is 0.5 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0.5 ns minimum from drive edge.
Referenced to drive edge.
MCE = 1, TFS enable and TFS valid follow t
Data Delay from Late External TFS or External RFS
with MCE = 1, MFD = 0
Data Enable from Late FS or MCE = 1, MFD = 0
RCLK
TCLK
RFS
TFS
DT
4
DT
1
RFS HOLD AFTER RCK WHEN MCE = 1, MFD = 0 IS 0.5ns MINIMUM FROM DRIVE EDGE.
DDTLFSE
TFS HOLD AFTER TCK FOR LATE EXTERNAL TFS IS 0.5ns MINIMUM FROM DRIVE EDGE.
EXTERNAL RFS WITH MCE = 1, MFD = 0
LATE EXTERNAL TFS
DRIVE
and t
DRIVE
DDTENFS
t
t
DDTENFS
SFSE/I
t
t
DDTENFS
SFSE/I
.
t
DDTLFSE
SAMPLE
Figure 17. External Late Frame Sync
FIRST BIT
SAMPLE
4
FIRST BIT
t
Rev. B | Page 24 of 48
HDTE/I
t
HDTE/I
Min
3.0
DRIVE
DRIVE
t
DDTE/I
t
DDTE/I
t
HFSE/I
5 V
t
HFSE/I
SECOND BIT
Max
14.1
1
SECOND BIT
1
Min
3.5
3.3 V
Max
14.3
Unit
ns
ns