AD14060BF-4 Analog Devices Inc, AD14060BF-4 Datasheet - Page 20

• Manufacturer Part Number: AD14060BF-4
• Description: IC DSP CMOS 32BIT 308CQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of AD14060BF-4

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 2MB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 308-CQFP
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Clock Freq (max): 40MHz
• Mips: 40
• Device Input Clock Speed: 40MHz
• Ram Size: 1.9073535156MB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 308
• Package Type: CQFP
• Lead Free Status / Rohs Status: Not Compliant

AD14060/AD14060L
Table 16. 1× CLK Speed Operation
Parameter
Receive
Timing Requirements:
t
t
t
t
t
Switching Characteristics:
t
t
t
t
Transmit
Timing Requirements:
t
t
Switching Characteristics:
t
t
t
t
t
t
t
t
Link Port Service Request Interrupts:
1× and 2× Speed Operations
Timing Requirements:
t
t
1
2
SLDCL
HLDCL
LCLKIW
LCLKRWL
LCLKRWH
DLAHC
DLALC
ENDLK
TDLK
SLACH
HLACH
DLCLK
DLDCH
HLDCH
LCLKTWL
LCLKTWH
DLACLK
ENDLK
TDLK
SLCK
HLCK
LACK goes low with t
Required only for interrupt recognition in the current cycle.
Data Setup before LCLK Low
Data Hold after LCLK Low
LCLK Period (1× Operation)
LCLK Width Low
LCLK Width High
LACK High Delay after CLKIN High
LACK Low Delay after LCLK High
LACK Enable from CLKIN
LACK Disable from CLKIN
LACK Setup before LCLK High
LACK Hold after LCLK High
LCLK Delay after CLKIN (1× Operation)
Data Delay after LCLK High
Data Hold after LCLK High
LCLK Width Low
LCLK Width High
LCLK Low Delay after LACK High
LDAT, LCLK Enable after CLKIN
LDAT, LCLK Disable after CLKIN
LACK/LCLK Setup before CLKIN Low
LACK/LCLK Hold after CLKIN Low
DLALC
relative to the rising edge of LCLK after the first nibble is received. LACK does not go low, if the receiver’s link buffer is not about to fill.
1
2
2
6
5
18 + DT/2
5 + DT/2
−7
−3
5 + DT/2
Min
3.5
3
t
−3
18
(t
(t
(t
10
2.5
CK
CK
CK
CK
/2) − 2
/2) − 2
/2) + 8.5
Rev. B | Page 20 of 48
5 V
Max
29.5 + DT/2
+13.5
21 + DT/2
16.5
3.5
(t
(t
(3 × t
21 + DT/2
CK
CK
/2) + 2
/2) + 2
CK
/2) + 17.5
Min
3
3
t
6
5
18 + DT/2
−3
5 + DT/2
20
−7
−3
(t
(t
(t
5 + DT/2
10
2.5
CK
CK
CK
CK
/2) − 1
/2) − 2.25
/2) + 8
3.3 V
Max
30 + DT/2
+13.5
21 + DT/2
17.5
3
(t
(t
(3 × t
18.25
21 + DT/2
CK
CK
/2) + 2.25
/2) + 1
CK
/2) +
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns