AD14060BF-4 Analog Devices Inc, AD14060BF-4 Datasheet - Page 36

• Manufacturer Part Number: AD14060BF-4
• Description: IC DSP CMOS 32BIT 308CQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of AD14060BF-4

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 2MB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 308-CQFP
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Clock Freq (max): 40MHz
• Mips: 40
• Device Input Clock Speed: 40MHz
• Ram Size: 1.9073535156MB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 308
• Package Type: CQFP
• Lead Free Status / Rohs Status: Not Compliant

AD14060/AD14060L
Bus locking is possible, allowing indivisible read-modify-write
sequences for semaphores. In either the fixed or rotating
priority scheme, it is also possible to limit the number of cycles
that the master can use to control the bus. The AD14060/
AD14060L provides the option of using the core priority access
(CPA) mode of the SHARC. Using the CPA signal allows
external bus accesses by the core processor of a slave SHARC to
take priority over ongoing DMA transfers. Also, each SHARC
can broadcast write to all other SHARCs simultaneously,
allowing the implementation of reflective semaphores.
The bus master can communicate with slave SHARCs by
writing messages to their internal IOP registers. The MSRG0 to
MSRG7 registers are general-purpose registers that can be used
for convenient message passing, semaphores, and resource
sharing among the SHARCs. For message passing, the master
communicates with a slave by writing and/or reading any of the
eight message registers on the slave. For vector interrupts, the
master can issue a vector interrupt to a slave by writing the
address of an interrupt service routine to the slave’s VIRPT
register. This causes an immediate high priority interrupt on the
slave, which, when serviced, causes it to branch to the specified
service routine.
MULTIPROCESSOR
MEMORY SPACE
MEMORY SPACE
(INDIVIDUAL
INTERNAL
SHARCs)
TO AD14060
TO AD14060
EXTERNAL
INTERNAL
NORMAL WORD ADDRESSING: 32-BIT DATA WORDS
SHORT WORD ADDRESSING: 16-BIT DATA WORDS
NORMAL WORD ADDRESSING
SHORT WORD ADDRESSING
INTERNAL MEMORY SPACE
INTERNAL MEMORY SPACE
INTERNAL MEMORY SPACE
INTERNAL MEMORY SPACE
INTERNAL MEMORY SPACE
INTERNAL MEMORY SPACE
BROADCAST WRITE
IOP REGISTERS
OF ADSP-2106x
OF ADSP-2106x
OF SHARC_A
OF SHARC_B
OF SHARC_C
OF SHARC_D
ADSP-2106xs
ID = 001
ID = 010
ID = 011
ID = 100
ID = 101
ID = 110
TO ALL
Figure 23. AD14060/AD14060L Memory Map
48-BIT INSTRUCTION WORDS
Rev. B | Page 36 of 48
0x0030 0000
0x0038 0000
0x003F FFFF
0x0004 0000
0x0008 0000
0x0010 0000
0x0018 0000
0x0020 0000
0x0028 0000
0x0000 0000
0x0002 0000
OFF-MODULE MEMORY AND PERIPHERALS
INTERFACE
The AD14060/AD14060L’s external port provides the interface
to off-module memory and peripherals (see Figure 24). This
port consists of the complete external port bus of the SHARC,
bused in common among the four SHARCs.
The 4-gigaword off-module address space is included in the
ADSP-14060’s unified address space. Addressing of external
memory devices is facilitated by each SHARC internally
decoding the high-order address lines to generate memory-
bank select signals. Separate control lines are also generated for
simplified addressing of page-mode DRAM. The AD14060/
AD14060L also supports programmable memory wait states
and external memory acknowledge controls to allow interfacing
to DRAM and peripherals with variable access, hold, and
disable time requirements.
EXTERNAL
MEMORY
SPACE
NONBANKED
(OPTIONAL)
BANK 0
BANK 1
BANK 2
BANK 3
DRAM
0x0040 0000
0xFFFF FFFF
BANK SIZE IS
SELECTED BY
MSIZE BIT FIELD
OF SYSCON
REGISTER
MS
MS
MS
MS
0
1
2
3