EPM570GF100C5N Altera, EPM570GF100C5N Datasheet - Page 3

IC MAX II CPLD 570 LE 100-FBGA

EPM570GF100C5N

Manufacturer Part Number
EPM570GF100C5N
Description
IC MAX II CPLD 570 LE 100-FBGA
Manufacturer
Altera
Series
MAX® IIr

Specifications of EPM570GF100C5N

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
5.4ns
Voltage Supply - Internal
1.71 V ~ 1.89 V
Number Of Logic Elements/blocks
570
Number Of Macrocells
440
Number Of I /o
76
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-FBGA
Voltage
1.8V
Memory Type
FLASH
Number Of Logic Elements/cells
570
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
544-1730

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0
EPM2210G &
EPM1270G
Brown-out
Voltage Issue
Altera Corporation
Note to
(1)
MAX IIG
Table 2. Recommended V
Device and VCCINT Operating
Rise times are measured from 10% to 90% of the stead-state operating voltage.
Table
2:
Voltage
f
CCINT
The MAX II POR circuitry is enhanced in later revisions to withstand
non-monotonic, slow rise times in the revision codes that are shown in
Table
before the fab code (first two alphanumeric characters) in the data code
printed on the top side of the device.
top side date code.
Figure 1. MAX II Device Top Side
The POR circuitry monitors V
brown-out conditions. During normal user-mode operation, the POR
circuit resets the SRAM configuration and tri-states the device I/O pins
when V
brown-out trigger voltage rises to 1.55 V on MAX IIG devices when the
optional DEV_OE feature/pin is de-asserted or during in-system
programming.
For more information on POR trip voltages and diagrams, see the
Hot-Socketing & Power-On Reset in MAX II Devices chapter of the MAX II
Handbook.
For EPM2210G and EPM1270G devices, if the AC switching current on
the device’s V
Table 3
before in-system programming begins, the brown-out trigger voltage can
rise as high as 1.7 V. This value is near the minimum operating voltage
(1.71 V) of the 1.8-V EPM2210G and EPM1270G devices and can lead to
unintended device reset during user-mode operation or a failed in-
system programming attempt. I
Rise Times and V
1. The die revision is identified by the alphanumeric character (Z)
immediately before DEV_OE de-asserts (tri-state all I/O pins) or
CCINT
Recommended V
falls approximately to or below 1.4 V. This POR circuit
CCINT
<= 540 µs
CCINT
supply (I
(1)
Noise/Dip Free Window (Continued)
CCINT
EPM2210G & EPM1270G Brown-out Voltage Issue
A Xβ Z ## ####
Rise Time
CCINT
CCINT
CCINT
) is more than the thresholds shown in
Die Revision
(but not V
Figure 1
is a function of logic element (LE)
Recommended POR Dip/Noise
CCIO
shows a MAX II device's
) voltage to detect
Free Window
1.3-1.65V
Preliminary
3

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