MT41J256M8HX-15E IT:D Micron Technology Inc, MT41J256M8HX-15E IT:D Datasheet - Page 191

• Manufacturer Part Number: MT41J256M8HX-15E IT:D
• Description: MICMT41J256M8HX-15E_IT:D 2GB DDR3 SDRAM
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J256M8HX-15E IT:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: -40C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

Dynamic ODT
Functional Description
Table 84: Dynamic ODT Specific Parameters
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
ODTLcwn4
ODTLcwn8
ODTLcnw
Symbol
t
ADC
Change from R
Change from R
Change from R
R
TT
Description
R
R
TT,nom
TT,nom
change skew
R
TT(WR)
In certain application cases, and to further enhance signal integrity on the data bus, it is
desirable that the termination strength of the DDR3 SDRAM can be changed without
issuing an MRS command, essentially changing the ODT termination on the fly. With
dynamic ODT (R
dynamic ODT (R
to nominal ODT (R
supported by the dynamic ODT feature, as described below.
The dynamic ODT mode is enabled if either MR2[9] or MR2[10] is set to 1. Dynamic
ODT is not supported during DLL disable mode so R
ic ODT function is described below:
• Two R
• During DRAM operation without READ or WRITE commands, the termination is con-
• When a WRITE command (WR, WRAP, WRS4, WRS8, WRAPS4, WRAPS8) is registered,
ODT is constrained during writes and when dynamic ODT is enabled (see Table 84
(page 191)). ODT timings listed in Table 83 (page 190) also apply to dynamic ODT mode.
– The value for R
– The value for R
trolled
– Nominal termination strength R
– Termination on/off timing is controlled via the ODT ball and latencies ODTL on
and if dynamic ODT is enabled, the ODT termination is controlled
– A latency of ODTLcnw after the WRITE command: termination strength R
– A latency of ODTLcwn8 (for BL8, fixed or OTF) or ODTLcwn4 (for BC4, fixed or
– On/off termination timing is controlled via the ODT ball and determined by ODTL
– During the
(BC4)
(BL8)
and ODTL off
switches to R
OTF) after the WRITE command: termination strength R
R
on, ODTL off, ODTH4, and ODTH8
TT,nom
TT(WR)
TT(WR)
TT,nom
TT
to
to
to
values are available—R
t
ODTLcnw completed
ADC transition window, the value of R
TT(WR)
TT(WR)
Write registration
Write registration
Write registration
TT(WR)
TT,nom
TT,nom
TT(WR)
Begins at
) enabled, the DRAM switches from nominal ODT (R
) when beginning a WRITE burst and subsequently switches back
) at the completion of the WRITE burst. This requirement is
is preselected via MR2[10, 9]
is preselected via MR1[9, 6, 2]
191
TT,nom
TT,nom
R
R
R
R
TT
TT
TT
TT
Micron Technology, Inc. reserves the right to change products or specifications without notice.
switched from R
switched from R
switched from R
and R
transition complete
Defined to
is used
to R
to R
to R
TT(WR)
2Gb: x4, x8, x16 DDR3 SDRAM
TT,nom
TT,nom
TT(WR)
TT(WR)
TT
TT,nom
TT(WR)
TT(WR)
is undefined
must be disabled. The dynam-
TT(WR)
© 2006 Micron Technology, Inc. All rights reserved.
Definition for All
DDR3 Speed Bins Units
4
6
0.5
t
t
CK + ODTL off
CK + ODTL off
t
switches back to
CK ± 0.2
WL - 2
Dynamic ODT
t
TT,nom
CK
TT,nom
) to
t
t
t
t
CK
CK
CK
CK