MT41J256M8HX-15E IT:D Micron Technology Inc, MT41J256M8HX-15E IT:D Datasheet - Page 127

• Manufacturer Part Number: MT41J256M8HX-15E IT:D
• Description: MICMT41J256M8HX-15E_IT:D 2GB DDR3 SDRAM
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J256M8HX-15E IT:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: -40C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

Write Leveling Procedure
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
A memory controller initiates the DRAM write leveling mode by setting MR1[7] to a 1,
assuming the other programable features (MR0, MR1, MR2, and MR3) are first set and
the DLL is fully reset and locked. The DQ balls enter the write leveling mode going from
a High-Z state to an undefined driving state, so the DQ bus should not be driven. Dur-
ing write leveling mode, only the NOP or DES commands are allowed. The memory
controller should attempt to level only one rank at a time; thus, the outputs of other
ranks should be disabled by setting MR1[12] to a 1 in the other ranks. The memory con-
troller may assert ODT after a
ODT transition. ODT should be turned on prior to DQS being driven LOW by at least
ODTL on delay (WL - 2
lay requirement.
The memory controller may drive DQS LOW and DQS# HIGH after
been satisfied. The controller may begin to toggle DQS after
is DQS transitioning from a LOW state to a HIGH state with DQS# transitioning from a
HIGH state to a LOW state, then both transition back to their original states). At a mini-
mum, ODTL on and
After
troller may provide either a single DQS toggle or multiple DQS toggles to sample CK for
a given DQS-to-CK skew. Each DQS toggle must not violate
(MIN) specifications.
during write leveling mode. The DQS must be able to distinguish the CK’s rising edge
within
the associated DQS rising edge CK capture within
drive LOW when DQS is toggling must be LOW within
isfied (the prime DQ going LOW). As previously noted, DQS is an input and not an
output during this process. Figure 47 (page 128) depicts the basic timing parameters
for the overall write leveling procedure.
The memory controller will likely sample each applicable prime DQ state and deter-
mine whether to increment or decrement its DQS delay setting. After the memory
controller performs enough DQS toggles to detect the CK’s 0-to-1 transition, the memo-
ry controller should lock the DQS delay setting for that DRAM. After locking the DQS
setting, leveling for the rank will have been achieved, and the write leveling mode for
the rank should be disabled or reprogrammed (if write leveling of another rank follows).
t
WLMRD and a DQS LOW preamble (
t
WLS and
t
WLH. The prime DQ will output the CK’s status asynchronously from
t
AON must be satisfied at least one clock prior to DQS toggling.
t
DQSL (MAX) and
t
CK), provided it does not violate the aforementioned
127
t
MOD delay as the DRAM will be ready to process the
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
DQSH (MAX) specifications are not applicable
t
WPRE) have been satisfied, the memory con-
2Gb: x4, x8, x16 DDR3 SDRAM
t
WLO. The remaining DQ that always
t
WLOE after the first
t
t
DQSL (MIN) and
WLMRD (one DQS toggle
© 2006 Micron Technology, Inc. All rights reserved.
t
WLDQSEN has
Write Leveling
t
WLO is sat-
t
MOD de-
t
DQSH