MT41J256M8HX-15E IT:D Micron Technology Inc, MT41J256M8HX-15E IT:D Datasheet - Page 138

• Manufacturer Part Number: MT41J256M8HX-15E IT:D
• Description: MICMT41J256M8HX-15E_IT:D 2GB DDR3 SDRAM
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J256M8HX-15E IT:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: -40C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

Output Drive Strength
OUTPUT ENABLE/DISABLE
TDQS Enable
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
If the DLL is enabled prior to entering self refresh mode, the DLL is automatically disa-
bled when entering SELF REFRESH operation and is automatically reenabled and reset
upon exit of SELF REFRESH operation. If the DLL is disabled prior to entering self re-
fresh mode, the DLL remains disabled even upon exit of SELF REFRESH operation until
it is reenabled and reset.
The DRAM is not tested to check—nor does Micron warrant compliance with—normal
mode timings or functionality when the DLL is disabled. An attempt has been made to
have the DRAM operate in the normal mode where reasonably possible when the DLL
has been disabled; however, by industry standard, a few known exceptions are defined:
• ODT is not allowed to be used
• The output data is no longer edge-aligned to the clock
• CL and CWL can only be six clocks
When the DLL is disabled, timing and functionality can vary from the normal operation
specifications when the DLL is enabled (see DLL Disable Mode (page 119)). Disabling
the DLL also implies the need to change the clock frequency (see Input Clock Frequen-
cy Change (page 123)).
The DDR3 SDRAM uses a programmable impedance output buffer. The drive strength
mode register setting is defined by MR1[5, 1]. RZQ/7 (34Ω [NOM]) is the primary output
driver impedance setting for DDR3 SDRAM devices. To calibrate the output driver impe-
dance, an external precision resistor (RZQ) is connected between the ZQ ball and V
The value of the resistor must be 240Ω ±1%.
The output impedance is set during initialization. Additional impedance calibration up-
dates do not affect device operation, and all data sheet timings and current specifica-
tions are met during an update.
To meet the 34Ω specification, the output drive strength must be set to 34Ω during initi-
alization. To obtain a calibrated output driver impedance after power-up, the DDR3
SDRAM needs a calibration command that is part of the initialization and reset procedure.
The OUTPUT ENABLE function is defined by MR1[12], as shown in Figure 54
(page 137). When enabled (MR1[12] = 0), all outputs (DQ, DQS, DQS#) function when in
the normal mode of operation. When disabled (MR1[12] = 1), all DDR3 SDRAM outputs
(DQ and DQS, DQS#) are tri-stated. The output disable feature is intended to be used
during Idd characterization of the READ current and during
eling) only.
Termination data strobe (TDQS) is a feature of the x8 DDR3 SDRAM configuration that
provides termination resistance (R
tions. TDQS is not supported in x4 or x16 configurations. When enabled via the mode
register (MR1[11]), the R
TDQS#. In contrast to the RDQS function of DDR2 SDRAM, DDR3’s TDQS provides the
termination resistance R
provided by TDQS; thus, Ron does not apply to TDQS and TDQS#. The TDQS and DM
TT
TT
that is applied to DQS and DQS# is also applied to TDQS and
only. The OUTPUT DATA STROBE function of RDQS is not
138
TT
) and may be useful in some system configura-
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2Gb: x4, x8, x16 DDR3 SDRAM
Mode Register 1 (MR1)
t
DQSS margining (write lev-
© 2006 Micron Technology, Inc. All rights reserved.
SSQ
.