LC5512MV-45FN484C Lattice, LC5512MV-45FN484C Datasheet - Page 46

• Manufacturer Part Number: LC5512MV-45FN484C
• Description: CPLD ispXPLD™ 5000MV Family 150K Gates 512 Macro Cells 275MHz EECMOS Technology 3.3V 484-Pin BGA
• Manufacturer: Lattice

Specifications of LC5512MV-45FN484C

• Package: 484BGA
• Family Name: ispXPLD™ 5000MV
• Device System Gates: 150000
• Number Of Macro Cells: 512
• Maximum Propagation Delay Time: 4.5 ns
• Number Of User I/os: 253
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 275 MHz
• Number Of Product Terms Per Macro: 160
• Memory Type: EEPROM/SRAM
• Ram Bits: 262144
• Operating Temperature: 0 to 90 °C

ispXPLD 5000MX Family Timing Adders (Continued)
Lattice Semiconductor
HSTL_I_out
HSTL_III_out
HSTL_IV_out
LVDS_out
LVPECL_out
PCI_out
SSTL2_I_out
SSTL2_II_out
SSTL3_I_out
SSTL3_II_out
Parameter
Using HSTL 2.5V,
Class I
Using HSTL 2.5V,
Class III
Using HSTL 2.5V,
Class IV
Using Low
Voltage Differen-
tial Signaling
(LVDS)
Using Low
Voltage PECL
Using PCI
Standard
Using SSTL 2.5V,
Class I
Using SSTL 2.5V,
Class II
Using SSTL 3.3V,
Class I
Using SSTL 3.3V,
Class II
Description
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Param.
IOBUF,
IOEN
IODIS
IOBUF,
IOEN
IODIS
IOBUF,
IOEN
IODIS
IOBUF,
IOEN
IODIS
IOBUF,
IOEN
IODIS
IOBUF,
IOEN
IODIS
IOBUF,
IOEN
IODIS
IOBUF,
IOEN
IODIS
IOBUF,
IOEN
IODIS
IOBUF,
IOEN
IODIS
Base
,
,
,
,
,
,
,
,
,
,
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
—
—
—
—
—
—
—
—
—
—
-4
42
0.5
0.6
0.6
0.8
0.3
0.6
0.3
0.5
0.2
0.4
—
—
—
—
—
—
—
—
—
—
-45
ispXPLD 5000MX Family Data Sheet
0.5
0.6
0.6
0.8
0.3
0.6
0.3
0.5
0.2
0.4
—
—
—
—
—
—
—
—
—
—
-5
0.5
0.6
0.6
0.8
0.3
0.6
0.3
0.5
0.2
0.4
—
—
—
—
—
—
—
—
—
—
-52
0.5
0.6
0.6
0.8
0.3
0.6
0.3
0.5
0.2
0.4
—
—
—
—
—
—
—
—
—
—
-75
0.5
0.6
0.6
0.8
0.3
0.6
0.3
0.5
0.2
0.4
Timing v.1.8
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns