LC5512MV-45FN484C Lattice, LC5512MV-45FN484C Datasheet - Page 79

• Manufacturer Part Number: LC5512MV-45FN484C
• Description: CPLD ispXPLD™ 5000MV Family 150K Gates 512 Macro Cells 275MHz EECMOS Technology 3.3V 484-Pin BGA
• Manufacturer: Lattice

Specifications of LC5512MV-45FN484C

• Package: 484BGA
• Family Name: ispXPLD™ 5000MV
• Device System Gates: 150000
• Number Of Macro Cells: 512
• Maximum Propagation Delay Time: 4.5 ns
• Number Of User I/os: 253
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 275 MHz
• Number Of Product Terms Per Macro: 160
• Memory Type: EEPROM/SRAM
• Ram Bits: 262144
• Operating Temperature: 0 to 90 °C

Lattice Semiconductor
ispXPLD 5768MX Logic Signal Connections (Continued)
Global Clock LVDS pair options: GCLK0 and GCLK1, as well as GCLK2 and GCLK3, can be paired together to
receive differential clocks; where GCLK0 and GCLK3 are the positive LVDS inputs.
sysIO Bank LVDS Pair
0
0
126N
126P
Primary Macrocell/
Function
S26
S24
Macrocell 1
S13
S12
Alternate Outputs
75
Macrocell 2
-
-
ispXPLD 5000MX Family Data Sheet
Alternate
Inputs
S27
S25
Ball Number
256 fpBGA
—
—
Ball Number
484 fpBGA
C4
D5