LC5512MV-45FN484C Lattice, LC5512MV-45FN484C Datasheet - Page 35

• Manufacturer Part Number: LC5512MV-45FN484C
• Description: CPLD ispXPLD™ 5000MV Family 150K Gates 512 Macro Cells 275MHz EECMOS Technology 3.3V 484-Pin BGA
• Manufacturer: Lattice

Specifications of LC5512MV-45FN484C

• Package: 484BGA
• Family Name: ispXPLD™ 5000MV
• Device System Gates: 150000
• Number Of Macro Cells: 512
• Maximum Propagation Delay Time: 4.5 ns
• Number Of User I/os: 253
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 275 MHz
• Number Of Product Terms Per Macro: 160
• Memory Type: EEPROM/SRAM
• Ram Bits: 262144
• Operating Temperature: 0 to 90 °C

Lattice Semiconductor
Timing Model
The task of determining timing in a ispXPLD 5000MX device is relatively simple. The timing model show in
Figure 20 shows the specific delay paths. Once the implementation of a given function is determined either con-
ceptually or from the software report file, the delay path of a function can easily be determined from the timing
model. The Lattice design tools report the timing delays based on the same timing model. Note that internal timing
parameters are for reference only, and are not tested. The external timing parameters are tested and guaranteed
for every device.
Figure 20. ispXPLD 5000MX Timing Model Diagram
GCLK
RST
OE
IN
From Feedback
t
GCLK _IN
t
t
GOE
t
t
t
t
t
RST
IOI
IOI
IOI
IN
IOI
t
PLL _SEC_DELAY
t
PLL _DELAY
t
t
INREG
t
INDIO
GCLK
Path only available for
t
ROUTEMF
t
ROUTE
t
t
BLA
CASC
FIFO Flags
Functions
Memory
3
CLK, CE and Reset Only
mode. Refer to timing tables for details.
Some paths not available in memory
t
t
CICOMFB
CICOMC
t
t
t
t
t
PTCLK
t
PTSA
EXP
SUM
t
BCLK
t
PDb
PTSR
BSR
31
t
t
t
GPTOE
SPTOE
PTOE
ispXPLD 5000MX Family Data Sheet
DATA
C.E.
S/R
t
MC Reg.
PDi
Q
t
OSA
t
FBK
t
t
t
t
BUF
IOO
DIS
EN
Feedback
OUT