ISPLSI 1048E-70LQ Lattice, ISPLSI 1048E-70LQ Datasheet - Page 2

• Manufacturer Part Number: ISPLSI 1048E-70LQ
• Description: CPLD ispLSI® 1000E Family 8K Gates 192 Macro Cells 70MHz EECMOS Technology 5V 128-Pin PQFP
• Manufacturer: Lattice

Specifications of ISPLSI 1048E-70LQ

• Package: 128PQFP
• Family Name: ispLSI® 1000E
• Device System Gates: 8000
• Number Of Macro Cells: 192
• Maximum Propagation Delay Time: 18.5 ns
• Number Of User I/os: 96
• Number Of Logic Blocks/elements: 48
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 70 MHz
• Operating Temperature: 0 to 70 °C

Figure 1. ispLSI 1048E Functional Block Diagram
The device also has 96 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, registered in-
put,
I/O pin with 3-state control. The signal levels are TTL
compatible voltages and the output drivers can source 4
mA or sink 8 mA. Each output can be programmed
independently for fast or slow output slew rate to mini-
mize overall output switching noise.
Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock (see
figure 1). The outputs of the eight GLBs are connected to
a set of 16 universal I/O cells by the ORP. Each ispLSI
1048E device contains six Megablocks.
MODE/IN 1
Functional Block Diagram
SDI/IN 0
RESET
GOE 0
GOE 1
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
ispEN
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
latched
Megablock
Logic Blocks
Generic
(GLBs)
IN 2
input,
A1
A2
A3
A4
A5
A6
A7
A0
SDO/
IN 3
I/O
16
B0
I/O
17
I/O
95
I/O
F7
18
output
I/O
94
B1
I/O
19
I/O
93
F6
Output Routing Pool (ORP)
I/O
92
I/O
20
B2
I/O
21
Output Routing Pool (ORP)
I/O
91
F5
I/O
22
I/O
90
B3
Input Bus
I/O
23
or
I/O
89
F4
I/O
Input Bus
88
I/O
24
B4
I/O
25
bi-directional
I/O
87
F3
I/O
26
I/O
B5
86
I/O
27
I/O
85
F2
I/O
84
I/O
28
B6
I/O
29
I/O
83
F1
I/O
30
B7
I/O
82
I/O
31
I/O
81
F0
I/O
80
Routing
Global
(GRP)
Pool
IN
2
4
IN
11
SCLK/
10
IN 5
The GRP has, as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 1048E device are selected using the
Clock Distribution Network. Four dedicated clock pins
(Y0, Y1, Y2 and Y3) are brought into the distribution
network, and five clock outputs (CLK 0, CLK 1, CLK 2,
IOCLK 0 and IOCLK 1) are provided to route clocks to the
GLBs and I/O cells. The Clock Distribution Network can
also be driven from a special clock GLB (D0). The logic
of this GLB allows the user to create an internal clock
from a combination of internal signals within the device.
IN
I/O
32
Specifications ispLSI 1048E
C0
I/O
33
I/O
79
E7
I/O
34
I/O
78
C1
I/O
35
I/O
77
E6
Output Routing Pool (ORP)
I/O
76
I/O
36
C2
I/O
37
Output Routing Pool (ORP)
I/O
75
E5
I/O
38
I/O
C3
74
Input Bus
I/O
39
I/O
73
Input Bus
E4
I/O
72
I/O
40
C4
I/O
41
I/O
71
E3
I/O
42
C5
I/O
70
I/O
43
I/O
69
E2
I/O
68
I/O
C6
44
I/O
45
I/O
67
E1
I/O
46
C7
I/O
66
I/O
47
I/O
65
E0
I/O
64
IN
9
Distribution
Network
Y
0
D6
D5
D4
D3
D2
D1
D0
D7
Clock
IN
8
Y
1
Y
2
0139F(2)-48B-isp
Y
3
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
IN 7
IN 6
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48