ISPLSI 1048E-70LQ Lattice, ISPLSI 1048E-70LQ Datasheet - Page 12

• Manufacturer Part Number: ISPLSI 1048E-70LQ
• Description: CPLD ispLSI® 1000E Family 8K Gates 192 Macro Cells 70MHz EECMOS Technology 5V 128-Pin PQFP
• Manufacturer: Lattice

Specifications of ISPLSI 1048E-70LQ

• Package: 128PQFP
• Family Name: ispLSI® 1000E
• Device System Gates: 8000
• Number Of Macro Cells: 192
• Maximum Propagation Delay Time: 18.5 ns
• Number Of User I/os: 96
• Number Of Logic Blocks/elements: 48
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 70 MHz
• Operating Temperature: 0 to 70 °C

Power consumption in the ispLSI 1048E device depends
on two primary factors: the speed at which the device is
operating and the number of Product Terms used.
Figure 3. Typical Device Power Consumption vs fmax
I CC can be estimated for the ispLSI 1048E using the following equation:
I CC = 20 + (# of PTs * 0.42) + (# of nets * Max. freq * 0.010)
Where:
The I CC estimate is based on typical conditions (V CC = 5.0V, room temperature) and an assumption of 4 GLB loads on
average exists. These values are for estimates only. Since the value of I CC is sensitive to operating conditions and the
program in the device, the actual I CC should be verified.
Maximum GRP Delay vs. GLB Loads
Power Consumption
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device
380
340
300
260
220
180
10
0
4
3
2
6
5
1
9
8
7
1
Notes: Configuration of twelve 16-bit counters,
4
20
8
40
Typical current at 5V, 25°C
16
f
max (MHz)
60
GLB Loads
80
ispLSI 1048E
12
100
32
Figure 3 shows the relationship between power and
operating speed.
Specifications ispLSI 1048E
120
140
0127A/1048E
48
ispLSI 1048E-50
ispLSI 1048E-70
ispLSI 1048E-90/100
ispLSI 1048E-125
0127B/1048E