ISPLSI 1048E-70LQ Lattice, ISPLSI 1048E-70LQ Datasheet - Page 13

• Manufacturer Part Number: ISPLSI 1048E-70LQ
• Description: CPLD ispLSI® 1000E Family 8K Gates 192 Macro Cells 70MHz EECMOS Technology 5V 128-Pin PQFP
• Manufacturer: Lattice

Specifications of ISPLSI 1048E-70LQ

• Package: 128PQFP
• Family Name: ispLSI® 1000E
• Device System Gates: 8000
• Number Of Macro Cells: 192
• Maximum Propagation Delay Time: 18.5 ns
• Number Of User I/os: 96
• Number Of Logic Blocks/elements: 48
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 70 MHz
• Operating Temperature: 0 to 70 °C

Pin Description
I/O 0 - I/O 5
I/O 6 - I/O 11
I/O 12 - I/O 17
I/O 18 - I/O 23
I/O 24 - I/O 29
I/O 30 - I/O 35
I/O 36 - I/O 41
I/O 42 - I/O 47
I/O 48 - I/O 53
I/O 54 - I/O 59
I/O 60 - I/O 65
I/O 66 - I/O 71
I/O 72 - I/O 77
I/O 78 - I/O 83
I/O 84 - I/O 89
I/O 90 - I/O 95
GOE0, GOE1
IN 2, IN 4
IN 6 - IN 11
ispEN
SDI/IN 0
MODE/IN 1
SDO/IN 3
SCLK/IN 5
RESET
Y0
Y1
Y2
Y3
GND
VCC
1. Pins have dual function capability.
NAME
1
1
1
1
21,
27,
34,
40,
52,
58,
66,
72,
85,
91,
98,
104,
117,
123,
2,
8,
64,
47,
84,
18
20
46
50
78
19
15
83
80
79
1,
97,
16,
PQFP / TQFP PIN NUMBERS
22,
28,
35,
41,
53,
59,
67,
73,
86,
92,
99,
105,
118,
124,
3,
9,
114
51
110,
17,
112
48,
23,
29,
36,
42,
54,
60,
68,
74,
87,
93,
100,
106,
119,
125,
4,
10,
111,
33,
82,
24,
30,
37,
43,
55,
61,
69,
75,
88,
94,
101,
107,
120,
126,
5,
11,
115,
49,
113
25,
31,
38,
44,
56,
62,
70,
76,
89,
95,
102,
108,
121,
127,
6,
12,
116,
65,
26,
32,
39,
45,
57,
63,
71,
77,
90,
96,
103,
109,
122,
128,
7,
13
14
81,
13
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
Global Output Enable input pins.
Dedicated input pins to the device.
Input - Dedicated in-system programming enable input pin. This pin is
brought low to enable the programming mode. When low, the MODE,
SDI, SDO and SCLK controls become active.
Input - This pin performs two functions. When ispEN is logic low, it
functions as an input pin to load programming data into the device.
SDI/IN 0 also is used as one of the two control pins for the ISP state
machine. When ispEN is high, it functions as a dedicated input pin.
Input - This pin performs two functions. When ispEN is logic low, it
functions as pin to control the operation of the isp state machine. When
ispEN is high, it functions as a dedicated input pin.
Output/Input - This pin performs two functions. When ispEN is logic low,
it functions as an output pin to read serial shift register data. When
ispEN is high, it functions as a dedicated input pin.
Input - This pin performs two functions. When ispEN is logic low, it
functions as a clock pin for the Serial Shift Register. When ispEN is
high, it functions as a dedicated input pin.
Active Low (0) Reset pin which resets all of the GLB and I/O registers in
the device.
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all of the GLBs on the device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.
Ground (GND)
V
CC
Specifications ispLSI 1048E
DESCRIPTION
Table 2 - 0002C-48E