ispLSI 2096A-125LQ128 Lattice, ispLSI 2096A-125LQ128 Datasheet

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ispLSI 2096A-125LQ128

Manufacturer Part Number
ispLSI 2096A-125LQ128
Description
CPLD - Complex Programmable Logic Devices USE ispMACH 4000V
Manufacturer
Lattice
Datasheet

Specifications of ispLSI 2096A-125LQ128

Memory Type
EEPROM
Number Of Macrocells
96
Maximum Operating Frequency
125 MHz
Delay Time
10 ns
Number Of Programmable I/os
96
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Package / Case
PQFP-128
Mounting Style
SMD/SMT
Factory Pack Quantity
120
Supply Current
295 mA
Supply Voltage - Max
5.25 V
Supply Voltage - Min
4.75 V
• ENHANCEMENTS
• HIGH DENSITY PROGRAMMABLE LOGIC
• HIGH PERFORMANCE E
• IN-SYSTEM PROGRAMMABLE
• OFFERS THE EASE OF USE AND FAST SYSTEM
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
2096_09
Features
— 4000 PLD Gates
— 96 I/O Pins, Six Dedicated Inputs
— 96 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
— Small Logic Block Size for Random Logic
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-to-
— Reprogram Soldered Devices for Faster Prototyping
— Complete Programmable Device Can Combine
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
— Lead-Free Package Options
— ispLSI 2096A is Fully Form and Function Compatible
— ispLSI 2096A is Built on an Advanced 0.35 Micron
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
Machines, Address Decoders, etc.
f
t
Market and Improved Product Quality
Glue Logic and Structured Designs
Minimize Switching Noise
Interconnectivity
to the ispLSI 2096, with Identical Timing
Specifcations and Packaging
E
max = 125 MHz Maximum Operating Frequency
pd = 7.5 ns Propagation Delay
2
CMOS
®
Technology
2
CMOS
®
TECHNOLOGY
1
In-System Programmable High Density PLD
The ispLSI 2096 and 2096A are High Density Program-
mable Logic Devices. The devices contain 96 Registers,
96 Universal I/O pins, six Dedicated Input pins, three
Dedicated Clock Input pins, two dedicated Global OE
input pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 2096 and 2096A feature 5V in-
system programmability and in-system diagnostic
capabilities. The ispLSI 2096 and 2096A offer non-
volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
The basic unit of logic on these devices is the Generic
Logic Block (GLB). The GLBs are labeled A0, A1…C7
(Figure 1). There are a total of 24 GLBs in the ispLSI 2096
and 2096A devices. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Functional Block Diagram
Description
Output Routing Pool (ORP)
Output Routing Pool (ORP)
GLB
Logic
Array
ispLSI
D Q
D Q
D Q
D Q
Global Routing Pool
Output Routing Pool (ORP)
Output Routing Pool (ORP)
(GRP)
®
2096/A
August 2006
0919/2096

Related parts for ispLSI 2096A-125LQ128

ispLSI 2096A-125LQ128 Summary of contents

Page 1

... Features • ENHANCEMENTS — ispLSI 2096A is Fully Form and Function Compatible to the ispLSI 2096, with Identical Timing Specifcations and Packaging — ispLSI 2096A is Built on an Advanced 0.35 Micron E 2 CMOS ® Technology • HIGH DENSITY PROGRAMMABLE LOGIC — 4000 PLD Gates — 96 I/O Pins, Six Dedicated Inputs — ...

Page 2

Functional Block Diagram Figure 1. ispLSI 2096/A Functional Block Diagram Output Routing Pool (ORP) I I/O 1 I/O 2 I/O 3 I I/O 6 I/O 7 I I/O 10 I/O ...

Page 3

Absolute Maximum Ratings Supply Voltage V ...................................-0.5 to +7.0V cc Input Voltage Applied ........................ -2 Off-State Output Voltage Applied ..... -2 Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to 125°C ...

Page 4

... Typical values are and T = 25° Maximum I varies widely with specific device configuration and operating frequency. Refer to the Power Consumption CC section of this data sheet and the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum Specifications ispLSI 2096/A Figure 2 ...

Page 5

External Timing Parameters 4 TEST 2 PARAMETER # COND Data Propagation Delay, 4PT Bypass, ORP Bypass pd1 Data Propagation Delay pd2 f max A 3 Clock Frequency with Internal Feedback f max (Ext.) – ...

Page 6

Internal Timing Parameters 2 PARAMETER # Inputs t 20 Input Buffer Delay Dedicated Input Delay din GRP t 22 GRP Delay grp GLB Product Term Bypass Comb. Path Delay 4ptbpc t 4ptbpr 24 4 ...

Page 7

Timing Model I/O Cell Ded. In #21 I/O Delay I/O Pin #20 (Input) #45 Reset #43, 44 Y0,1,2 #42 GOE 0 Derivations of su, h and co from the Product Term Clock ...

Page 8

Power Consumption Power consumption in the ispLSI 2096 and 2096A de- vices depends on two primary factors: the speed at which the device is operating and the number of Product Terms Figure 4. Typical Device Power Consumption vs fmax 300 ...

Page 9

Pin Description NAME PQFP & TQFP PIN NUMBERS I I/O 5 21, 22, 23, I I/O 11 27, 28, 29, I I/O 17 34, 35, 36, I I/O 23 40, 41, 42, ...

Page 10

Pin Configuration ispLSI 2096/A 128-pin PQFP and TQFP Pinout Diagram GND ...

Page 11

... Discontinued per PCN #02-06. Contact Rochester Electronics for available inventory. Specifications ispLSI 2096/A – XXX COMMERCIAL ORDERING NUMBER 7.5 ispLSI 2096A-125LQ128 7.5 ispLSI 2096A-125LT128 ispLSI 2096A-100LQ128 10 10 ispLSI 2096A-100LT128 15 ispLSI 2096A-80LQ128 ispLSI 2096A-80LT128 15 7.5 ispLSI 2096-125LQ 7.5 ispLSI 2096-125LT ispLSI 2096-100LQ ...

Page 12

... Specifications ispLSI 2096/A COMMERCIAL ORDERING NUMBER 7.5 ispLSI 2096A-125LQN128 7.5 ispLSI 2096A-125LTN128 ispLSI 2096A-100LQN128 10 10 ispLSI 2096A-100LTN128 15 ispLSI 2096A-80LQN128 ispLSI 2096A-80LTN128 15 INDUSTRIAL ORDERING NUMBER 15 ispLSI 2096A-80LQN128I 15 ispLSI 2096A-80LTN128I Previous Lattice release. Updated for lead-free package options. 12 PACKAGE Lead-Free 128-Pin PQFP Lead-Free 128-Pin TQFP ...

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