ISPLSI 1048E-70LQ Lattice, ISPLSI 1048E-70LQ Datasheet - Page 11

• Manufacturer Part Number: ISPLSI 1048E-70LQ
• Description: CPLD ispLSI® 1000E Family 8K Gates 192 Macro Cells 70MHz EECMOS Technology 5V 128-Pin PQFP
• Manufacturer: Lattice

Specifications of ISPLSI 1048E-70LQ

• Package: 128PQFP
• Family Name: ispLSI® 1000E
• Device System Gates: 8000
• Number Of Macro Cells: 192
• Maximum Propagation Delay Time: 18.5 ns
• Number Of User I/os: 96
• Number Of Logic Blocks/elements: 48
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 70 MHz
• Operating Temperature: 0 to 70 °C

ispLSI 1048E Timing Model
1. Calculations are based upon timing specifications for the ispLSI 1048E-125.
Derivations of
Derivations of
GOE 0,1
Ded. In
I/O Pin
Reset
Y1,2,3
(Input)
Y0
t
t
t
t
t
t
h
co
su
h
co
#59
su
10.9 ns
2.2 ns
3.4 ns
3.5 ns
2.2 ns
9.6 ns
I/O Reg Bypass
D
RST
Register
Input
#28
#22
#23 - 27
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
t
I/O Cell
t
su,
su,
Clock (max) + Reg h - Logic
(
(#22 + #30 + #46) + (#41) - (#22 + #30 + #37)
(0.3 + 2.0 + 4.0) + (4.5) – (0.3 + 2.0 + 5.0)
Clock (max) + Reg co + Output
(
(#22 + #30 + #46) + (#42) + (#47 + #49)
(0.3 + 2.0 + 4.0) + (2.3) + (1.0 + 1.3)
Logic + Reg su - Clock (min)
(
(#22 + #30 + #37) + (#40) – (#54 + #42 + #56)
(0.3 + 2.0 + 5.0) + (0.1) – (0.9 + 2.3 + 0.8)
Clock (max) + Reg h - Logic
(
(#54 + #42 + #56) + (#41) – (#22 + #30 + #37)
(0.9 + 2.3 + 1.8) + (4.5) – (0.3 + 2.0 + 5.0)
Clock (max) + Reg co + Output
(
(#54 + #42 + #56) + (#42) + (#47 + #49)
(0.9 + 2.3 + 1.8) + (2.3) + (1.0 + 1.3)
Logic + Reg su - Clock (min)
(
(#22 + #30 + #37) + (#40) – (#22 + #30 + #46)
(0.3 + 2.0 + 5.0) + (0.1) – (0.3 + 2.0 + 2.9)
t
t
t
t
t
t
Q
iobp +
iobp +
iobp +
gy0(max) +
gy0(max) +
iobp +
t
t
h and
h and
t
t
t
t
grp4 +
grp4 +
grp4 +
grp4 +
t
t
co from the Clock GLB
co from the Product Term Clock
t
t
gco +
gco +
GRP Loading
#29, 31-33
Distribution
t
t
t
#55 - 58
t
ptck(max)) + (
20ptxor) + (
Delay
20ptxor) + (
GRP4
Clock
ptck(max)) + (
#30
GRP
#54
#53
t
t
gcp(max)) + (
gcp(max)) + (
t
t
gsu) – (
gsu) – (
t
t
gh) – (
gco) + (
Reg 4 PT Bypass
XOR Delays
Control
PTs
#44 - 46
t
t
Feedback
gh) – (
gco) + (
#36 - 38
20 PT
t
t
#35
#59
gy0(min) +
iobp +
t
#34
iobp +
t
1
11
orp +
RE
OE
CK
t
iobp +
t
orp +
Comb 4 PT Bypass
t
grp4 +
t
GLB
grp4 +
t
Specifications ispLSI 1048E
ob)
t
t
t
gco +
grp4 +
GLB Reg Bypass
ob)
1
D
RST
t
GLB Reg
ptck(min))
t
Table 2-0042/1048E
Delay
20ptxor)
#39
#40 - 43
t
gcp(min))
t
20ptxor)
Q
ORP Bypass
Delay
ORP
ORP
#48
#47
#49, 50
0491
#51, 52
I/O Cell
(Output)
I/O Pin