ISPLSI 1048E-70LQ Lattice, ISPLSI 1048E-70LQ Datasheet - Page 10

• Manufacturer Part Number: ISPLSI 1048E-70LQ
• Description: CPLD ispLSI® 1000E Family 8K Gates 192 Macro Cells 70MHz EECMOS Technology 5V 128-Pin PQFP
• Manufacturer: Lattice

Specifications of ISPLSI 1048E-70LQ

• Package: 128PQFP
• Family Name: ispLSI® 1000E
• Device System Gates: 8000
• Number Of Macro Cells: 192
• Maximum Propagation Delay Time: 18.5 ns
• Number Of User I/os: 96
• Number Of Logic Blocks/elements: 48
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 70 MHz
• Operating Temperature: 0 to 70 °C

1. Internal timing parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
PARAMETER
Internal Timing Parameters
Outputs
t
t
t
t
t
Clocks
t
t
t
t
t
Global Reset
t
ob
sl
oen
odis
goe
gy0
gy1/2
gcp
ioy2/3
iocp
gr
49 Output Buffer Delay
50 Output Slew Limited Delay Adder
51 I/O Cell OE to Output Enabled
52 I/O Cell OE to Output Disabled
53 Global OE
54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
55 Clock Delay, Y1 or Y2 to Global GLB Clock Line
56 Clock Delay, Clock GLB to Global GLB Clock Line
57 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
58 Clock Delay, Clock GLB to I/O Cell Global Clock Line
59 Global Reset to GLB and I/O Registers
#
1
DESCRIPTION
10
Specifications ispLSI 1048E
MIN.
2.8
2.8
0.8
0.1
0.8
–
–
–
–
–
–
-70
MAX.
12.0
2.2
6.9
6.9
5.1
4.5
2.8
2.8
1.8
0.6
1.8
MIN.
3.3
3.3
0.8
0.0
0.8
–
–
–
–
–
–
-50
MAX.
Table 2-0037B/1048E
12.0
3.2
7.9
7.9
8.1
3.3
3.3
1.8
0.7
1.8
7.5
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns