MT48H8M16LFB4-75 IT:J TR Micron Technology Inc, MT48H8M16LFB4-75 IT:J TR Datasheet - Page 58

• Manufacturer Part Number: MT48H8M16LFB4-75 IT:J TR
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M16LFB4-75 IT:J TR

• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 8/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 70mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

Concurrent Auto Precharge
READ With Auto Precharge
PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac
sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN
1. Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
command. A precharge of the bank/row that is addressed with the READ or WRITE
command is automatically performed upon completion of the READ or WRITE burst,
except in the continuous page burst mode, where auto precharge does not apply. In the
specific case of write burst mode set to single location access with burst length set to
continuous, the burst length setting is the overriding setting and auto precharge does
not apply. Auto precharge is nonpersistent in that it is either enabled or disabled for each
individual READ or WRITE command.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. The user must not issue another command to the same bank until the precharge
time (
issued at the earliest possible time, as described for each burst type in the Burst Type
section on page 38.
This device supports
a single WRITE with auto precharge, issued at
delayed until
Initiating an access command (READ or WRITE) to a second bank while an access
command with auto precharge enabled on a first bank is executing is not supported by
SDRAM, unless the SDRAM supports concurrent auto precharge. Micron SDRAM
supports concurrent auto precharge. Four cases where concurrent auto precharge
occurs are defined in the following sections; two are for READ with auto precharge, two
are for WRITE with auto precharge.
rupt a READ on bank n following the programmed CL. The precharge to bank n
begins when the READ to bank m is registered (see Figure 36 on page 59).
interrupt a READ on bank n when registered. DQM should be used two clocks prior to
the WRITE command to prevent bus contention. The precharge to bank n begins
when the WRITE to bank m is registered (see Figure 37 on page 59).
t
RP) is completed. This is determined as if an explicit PRECHARGE command was
t
RASmin has been satisfied.
t
RAS lock-out. In the case of a single READ with auto precharge, or
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
58
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RCDmin, the internal precharge will be
©2008 Micron Technology, Inc. All rights reserved.
Timing Diagrams