MT48H8M16LFB4-75 IT:J TR Micron Technology Inc, MT48H8M16LFB4-75 IT:J TR Datasheet - Page 19

• Manufacturer Part Number: MT48H8M16LFB4-75 IT:J TR
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M16LFB4-75 IT:J TR

• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 8/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 70mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

Table 11:
PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac
128mb_mobile_sdram_y35m__2.fm - Rev. E 4/09 EN
Parameter
Last data-in to burst STOP command
READ/WRITE command to READ/WRITE command
Last data-in to new READ/WRITE command
CKE to clock disable or power-down entry mode
Data-in to ACTIVE command
Data-in to PRECHARGE command
DQM to input data delay
DQM to data mask during WRITEs
DQM to data High-Z during READs
WRITE command to input data delay
LOAD MODE REGISTER command to ACTIVE or REFRESH
command
CKE to clock enable or power-down exit mode
Last data-in to PRECHARGE command
Data-out High-Z from PRECHARGE command
AC Functional Characteristics
Notes 1–5 apply to all parameters; notes appear on page 19
Notes:
10. For auto precharge mode, the precharge timing budget (
11. CLK must be toggled a minimum of two times during this period.
1. A full initialization sequence is required before proper device operation is ensured.
2. The minimum specifications are used only to indicate cycle time at which proper operation
3. In addition to meeting the transition rate specification, the clock and CKE must transit
4. Outputs measured for 1.8V at 0.9V with equivalent load:
5. AC timing tests have Vil and Vih with timing referenced to Vih/2 = crossover point. If the
6. The clock frequency must remain constant (stable clock is defined as a signal cycling within
7.
8. The 128Mb Mobile SDRAM requires 4096 AUTO REFRESH cycles every 64ms (
9. AC characteristics assume
over the full temperature range (–40°C ≤ T
between Vih and Vil (or between Vil and Vih) in a monotonic manner.
Test loads with full DQ driver strength. Performance will vary with actual system DQ bus
capacitive loading, termination, and programmed drive strength.
input transition time is longer than
Vih (MIN) and no longer at the Vih/2 crossover point.
timing constraints specified for the clock ball) during access or precharge states (READ,
WRITE, including
rate.
t
erence to Voh or Vol. The last valid data element will meet
a distributed AUTO REFRESH command every 15.6µs meets the refresh requirement and
ensures that each row is refreshed. Alternatively, 4096 AUTO REFRESH commands can be
issued in a burst at the minimum cycle rate (
ing must be derated. Input setup times require an additional 50ps for each 100 mV/ns
reduction in slew rate. Input hold times remain unchanged. If the slew rate exceeds 4.5V/ns,
functionality is uncertain.
-6, after the first clock delay and after the last WRITE is executed.
Q
HZ defines the time at which the output achieves the open circuit condition; it is not a ref-
20pF
t
WR, and PRECHARGE commands). CKE may be used to reduce the data
CL = 3
CL = 2
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
t
T = 1ns. For command and address input slew rates ≤0.5V/ns, tim-
19
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
BDL
CCD
CDL
CKED
DAL
DPL
DQD
DQM
DQZ
DWD
MRD
PED
RDL
ROH
t
T (MAX), then the timing is referenced at Vil (MAX) and
Micron Technology, Inc., reserves the right to change products or specifications without notice.
A
≤ +85°C industrial temperature) is ensured.
t
RFC), one time for every 64ms.
-6
1
1
1
1
5
2
0
0
2
0
2
1
2
3
2
t
RP) begins at 7.5ns for -75, 9ns for
Electrical Specifications
-75
t
OH before going High-Z.
1
1
1
1
5
2
0
0
2
0
2
1
2
3
2
©2008 Micron Technology, Inc. All rights reserved.
Unit
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
t
REF). Providing
Notes
14, 16
15, 16
15, 16
12
12
12
13
12
12
12
12
13
12