SCD240110QCM Intel, SCD240110QCM Datasheet - Page 81
SCD240110QCM
Manufacturer Part Number
SCD240110QCM
Description
Manufacturer
Intel
Datasheet
1.SCD240110QCM.pdf
(176 pages)
Specifications of SCD240110QCM
Operating Supply Voltage (max)
7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Lead Free Status / Rohs Status
Not Compliant
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6.3.4
Datasheet
Note: For the transparent bisync frames (receive only), the first DLE is not included in the CRC
At the end of a non-transparent frame:
At the end of a transparent frame:
calculation (except DLE-SYN, where the SYN is also not included.
Transparency Support
In transmit, the CD2401 generates CRC according to the previous illustrations, however the host
must manually insert the DLE in the data stream.
On receive, the CD2401 checks CRC according to the previous illustrations and strips the DLE
from the data stream.
BCC Computation Formulas
In Bisync mode, the CD2401 can use either CRC-16 or LRC. The mode used is determined by the
setting of the LRC bit (COR2[7]). CRC-16 uses the polynomial in the following equation, preset to
all zeroes.
LRC performs a parity check on each bit of each character in the frame in a longitudinal or
‘vertical’ manner. For example, in the following 3-byte frame, LRC with even parity is computed
as:
Character 1: 10010001
Character 2: 11000001
Character 3: 11000001
LRC:
Data
Data
Data
Data
Data
Data
Data
CRC
CRC
Data
Data
Data
Data
CRC Ends
10010001
SYN
Data
Data
Data
x**16 + x**15 + x**2 + 1
Data
DLE
DLE
DLE
CRC
ETX
ETB
ITB
Data
CRC
ETX
ETB
ITB
Multi-Protocol Communications Controller — CD2401
SYN
BCC
BCC
BCC
SYN
BCC
BCC
BCC
Data
CRC
BCC
BCC
BCC
BCC
BCC
BCC
Data
81
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