SCD240110QCM Intel, SCD240110QCM Datasheet - Page 106

• Manufacturer Part Number: SCD240110QCM
• Manufacturer: Intel

Specifications of SCD240110QCM

• Operating Supply Voltage (max): 7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / Rohs Status: Not Compliant

CD2401 — Multi-Protocol Communications Controller
8.2.7
106
Register Name: COR6
Register Description: Channel Option 6
Default Value: x’00
Access: Byte Read/Write
IgnCR
Bit 7
Channel Option Register 6 (COR6)
COR6 — Async Mode
CR is defined as 0D hex, NL as 0A hex, and NULL as 00 hex.
Bits 7:5
Bits 4:3
Bits 2:0
ICRNL
Bit 6
These three bits enable translation of received CR/NL characters as:
Break action
These bits determine the action taken after a BREAK condition is received.
Parity/framing error actions
These bits determine the action taken when a parity or framing error is received.
Following the generation of a BREAK exception interrupt, a receive exception inter-
rupt is generated with the Timeout bit (RISRl[7]) set when the end-of-break is
detected. The RET interrupt must be enabled (IER[5]) to enable this feature.
INLCF
Bit 5
IgnCr
IgnBrk
0
0
0
0
1
1
1
1
0
0
1
1
ICRNL
IgnBrk
0
0
1
1
0
0
1
1
Bit 4
NBrkInt
0
1
0
1
INLCR
0
1
0
1
0
1
0
1
Generate an exception interrupt.
Translate to a NULL character.
Reserved
Discard character.
NBrkInt
Bit 3
No special action on CR and NL.
NL translated to CR.
CR translated to NL.
CR translated to NL and NL translated to CR.
CR discarded.
CR discarded and NL translated to CR.
CR discarded.
CR discarded and NL translated to CR.
Function
ParMrk
Bit 2
Function
Motorola Hex Address: x’18
INPCK
Bit 1
Intel Hex Address: x’1B
Datasheet
ParInt
Bit 0