SCD240110QCM Intel, SCD240110QCM Datasheet - Page 63

• Manufacturer Part Number: SCD240110QCM
• Manufacturer: Intel

Specifications of SCD240110QCM

• Operating Supply Voltage (max): 7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / Rohs Status: Not Compliant

Datasheet
Table 8. Bit Rate Constants, CLK = 35 MHz (Sheet 2 of 2)
1.All divisors are in hexadecimal.
Transmit and receive data can be encoded/decoded in NRZ, NRZI, or Manchester formats. For
NRZI, at the start of transmission a learning data stream of contiguous zeros achieves bit
synchronization; for Manchester, an alternating pattern of ones and zeros is required.
NRZ, NRZI, and Manchester are data encoding schemes used in various synchronous protocols. In
NRZ, the signal condition represents the data type: high for logic 1 and low for logic 0. In NRZ-
and NRZI-type encoding, the transitions of the data stream occur at the beginning of the bit cell. In
NRZI, the signal condition switches to the opposite state to send a binary 0. In Manchester
encoding, the transitions are always in the middle of the bit cell: a high-to-low transition is made to
send a logic 1, and a low-to-high transition to send a logic 0.
encoding methods. The eight data bits are ‘0110010’.
Example 3
This example illustrates programming the DPLL at 128 kbps in NRZI mode using the internal
clock with a system clock frequency of 35 MHz.
Divisor loaded into R/TBPR = 33 or 22h.
Value loaded into RCOR = 28h to enable the DPLL, NRZI framing, and select Clk 0.
Example 4
This example illustrates programming the DPLL in 1 External Clock mode, with Manchester
encoding.
Divisor loaded into RBPR = 01h to enable 1 external clock.
Value loaded into RCOR = 36h to enable the DPLL, select Manchester framing, and external clock.
When using an n-times external clock, the highest possible clock frequency and largest divisor
combination is recommended. The frequency of an external clock should be less than the system
CLK input divided by 16, (that is, for 33-MHz operation, the data clock should be less than 2
MHz). Note that R/TBPR are 8-bit registers; therefore the largest divisor value is 255.
Use the following equation to compute the divisor value.
Bit Rate
4800
7200
9600
19200
38400
56000
64000
76800
115200
12800
134400
Divisor
e3
97
71
e3
71
4d
43
38
25
21
20
Multi-Protocol Communications Controller — CD2401
1
Clock
Clk 1
Clk 1
Clk 1
Clk 0
Clk 0
Clk 0
Clk 0
Clk 0
Clk 0
Clk 0
Clk 0
Figure 11
0.06%
0.06%
0.06%
0.06%
0.06%
0.16%
0.53%
0.06%
0.06%
0.53%
1.38%
Error
through
Figure 13
illustrate
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