SCD240110QCM Intel, SCD240110QCM Datasheet - Page 170
SCD240110QCM
Manufacturer Part Number
SCD240110QCM
Description
Manufacturer
Intel
Datasheet
1.SCD240110QCM.pdf
(176 pages)
Specifications of SCD240110QCM
Operating Supply Voltage (max)
7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Lead Free Status / Rohs Status
Not Compliant
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High-Impedance mode 19
host interface 35
host read and write cycles 35
host read/write 158
I
Idle in Mark mode 100
Idle mode 100
interrupt acknowledge 159
interrupts
K
keep and pass logic 42
L
Local Loopback mode 115
M
memory map 21
modes
170
acknowledge cycle 39
contexts and channels 38
groups and types 39
IACK cycles 41
keep and pass logic 42
multi–CD2401 systems 42
registers 38
systems with interrupt controllers 42
transmit and receive interrupt service re-
Addressing mode 94
Append mode 56
Async-HDLC/PPP mode 31, 102, 119,
Asynchronous DMA mode 57
Asynchronous mode 19, 27, 98, 101, 106,
Chain mode 48
Clock 19
DPLL mode 114
FCS mode 100
quests 41
122, 131
120, 130
multi–CD2401 systems 42
O
operations
ordering information example 168
P
package specifications 167
Parity mode 95
pin descriptions 16
pin diagram
pin functions
pin information 15
PPP mode 98
programming the PILR registers 41
Protocol mode 93
protocol processing 68
Flow Control Transparency (FCT) mode
HDLC 98
HDLC mode 27, 94, 96, 100, 120, 129
High-Impedance mode 19
Idle in Mark mode 100
Idle mode 100
Local Loopback mode 115
Parity mode 95
PPP 98
Protocol mode 93
Receive Transfer mode 93
Remote Loopback mode 97
SYN/Flag Hunt mode 118
Synchronous mode 100
Transmit Transfer mode 93
XON mode 97
BGR 58
DMA 44
DPLL 58
FIFO and timer 43
receive FIFO 43
transmit FIFO 43
CD2401 15
CD2401 16
101
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