SCD240110QCM Intel, SCD240110QCM Datasheet - Page 135

• Manufacturer Part Number: SCD240110QCM
• Manufacturer: Intel

Specifications of SCD240110QCM

• Operating Supply Voltage (max): 7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / Rohs Status: Not Compliant

8.5.3
8.5.3.1
8.5.3.2
Datasheet
Register Name: TPILR
Register Description: Transmit Priority Interrupt Match
Default Value: x’00
Access: Byte Read/Write
Register Name: TIR
Register Description: Transmit Interrupt
Default Value: None, value varies
Access: Byte Read only
Bit 7
Bit 7
Ten
Note: Bit 7 of this register always reads back as ‘0’. When each of the three PILRs are programmed with
Bits 2:0
Transmit Interrupt Registers
Transmit Priority Interrupt Level Register (TPILR)
This register must be initialized by the host to contain the codes that are presented on the address
bus by the host system to indicate which of the three CD2401 interrupt types (that is, modem,
transmit, or receive) is being acknowledged when IACKIN* is asserted. The CD2401 compares
bits 0–6 in this register with A[0–6] to determine if the acknowledge level is correct. The value
programmed in the MSB of this register has no effect on the IACK cycle.
TPILR must contain the code used to acknowledge transmit interrupts.
the same value, automatic internal prioritization is activated, with receive as the highest priority,
followed by transmit and modem.
Transmit Interrupt Register (TIR)
Bit 7
Bit 6
Bit 6
Tact
DMA buffer gaps [2:0]
These bits set the size of the optional gaps to be left in DMA buffer starting at the
current location before resuming data transfer. The CD2401 moves its buffer address
pointer forward the selected number of bytes. It does not write to any location ‘in the
gap’. If the gap is large enough to complete or extend beyond the end of the current
buffer, it completes and the gap continues in the other receive buffer. If the discard
exception character is not selected, the character where the exception occurred is
written to the buffer following the gap.
Transmit Enable
This bit is set by the CD2401 to initiate a transmit interrupt request sequence. It is
cleared during a valid transmit interrupt acknowledge cycle.
Bit 5
Bit 5
Teoi
User-Assigned Priority Match Value
Bit 4
Bit 4
0
Multi-Protocol Communications Controller — CD2401
Tvct [1]
Bit 3
Bit 3
Tvct [0]
Bit 2
Bit 2
Motorola Hex Address: x’EC
Motorola Hex Address: x’E0
Tcn [1]
Bit 1
Bit 1
Intel Hex Address: x’EE
Intel Hex Address: x’E2
Tcn [0]
Bit 0
Bit 0
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