HYB 39S128160CE-7.5 Infineon Technologies, HYB 39S128160CE-7.5 Datasheet
HYB 39S128160CE-7.5
Specifications of HYB 39S128160CE-7.5
Related parts for HYB 39S128160CE-7.5
HYB 39S128160CE-7.5 Summary of contents
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... CAS latency and speed grade of the device. Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single 3.3 V 0.3 V power supply and are available in TSOPII packages. INFINEON Technologies 128-MBit Synchronous DRAM • Multiple Burst Read with Single Write Operation Units • ...
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... Chip Select RAS Row Address Strobe CAS Column Address Strobe WE Write Enable A0 - A11 Address Inputs BA0, BA1 Bank Select INFINEON Technologies HYB 39S128400/800/160CT(L) 128-MBit Synchronous DRAM Description 143MHz 4B 133 MHz 4B 100 MHz 4B 143 MHz 4B 133 MHz 4B 100 MHz 4B 143 MHz 4B 133 MHz 4B ...
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... DQ5 N.C. DQ6 DQ3 V V SSQ SSQ DQ7 N. LDQM N. CAS CAS RAS RAS CS CS BA0 BA0 BA1 BA1 A10 A10 TSOPII-54 (10. 22.22 mm, 0.8 mm pitch) Pin Configuration for x4, x8 & x16 Organized 128M-DRAMs INFINEON Technologies N. DDQ N. DQ0 SSQ N. N. DDQ N. DQ1 SSQ N ...
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... Counter Row Decoder Memory Array Bank 0 4096 x 2048 x 4 Bit Input Buffer DQ0 - DQ3 Block Diagram: 32M x4 SDRAM ( addressing) INFINEON Technologies 128-MBit Synchronous DRAM Row Addresses A0 - A9, A11, AP A11, BA0, BA1 BA0, BA1 Column Address Row Address Buffer Buffer Row Decoder ...
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... Counter Row Decoder Memory Array Bank 0 4096 x 1024 x 8 Bit Input Buffer DQ0 - DQ7 Block Diagram: 16M x8 SDRAM ( addressing) INFINEON Technologies HYB 39S128400/800/160CT(L) 128-MBit Synchronous DRAM Row Addresses A0 - A9, AP A11, BA0, BA1 BA0, BA1 Column Address Row Address Buffer Buffer Row ...
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... Column Address Counter Row Decoder Memory Array Bank 0 4096 x 512 x 16 Bit Input Buffer DQ0 - DQ15 Block Diagram: 8M x16 SDRAM ( addressing) INFINEON Technologies HYB 39S128400/800/160CT(L) 128-MBit Synchronous DRAM Row Addresses A0 - A8, AP A11, BA0, BA1 BA0, BA1 Column Address Row Address Buffer Buffer ...
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... DQx Input Level – Output INFINEON Technologies HYB 39S128400/800/160CT(L) 128-MBit Synchronous DRAM The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. Activates the CLK signal when high and deactivates the CLK signal when low, thereby initiating either the Power Down mode, Suspend mode, or the Self Refresh mode ...
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... V Supply – – DDQ V SSQ INFINEON Technologies HYB 39S128400/800/160CT(L) 128-MBit Synchronous DRAM The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. In Write mode, DQM ...
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... This is the state of the banks designated by BA0, BA1 signals. 4. Power Down Mode can not entry in the burst cycle. When this command is asserted in the burst mode cycle the device is in clock suspend mode. INFINEON Technologies HYB 39S128400/800/160CT(L) 128-MBit Synchronous DRAM CKE ...
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... BA1 BA0 M11 M10 atency Latency Reserved Reserved Reserved INFINEON Technologies 128-MBit Synchronous DRAM CAS Latency BT B urst Typ Mode M3 Burst Read Burst Write 1 Burst Read Single Write B u rst L engt HYB 39S128400/800/160CT( Address Bus (Ax) Burst Length Mode Register (Mx) Type Sequential ...
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... Full page burst operation is only possible using sequential burst type and page length is a function of the I/O organisation and column addressing. Full page burst operation does not self terminate INFINEON Technologies HYB 39S128400/800/160CT(L) 128-MBit Synchronous DRAM ...
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... The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE are held high at a clock timing. The mode restores word line after the refresh and no external precharge INFINEON Technologies HYB 39S128400/800/160CT(L) 128-MBit Synchronous DRAM ...
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... CAS latency = 2, two clocks before the last data out for CAS latency = 3 and three clocks before the last data out for CAS latency = 4. Writes require a time delay t from the last data out to apply the precharge command. WR INFINEON Technologies HYB 39S128400/800/160CT(L) 128-MBit Synchronous DRAM t time is required between two automatic refreshes in a burst ...
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... If a Burst Stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is registered will be written to the memory. INFINEON Technologies HYB 39S128400/800/160CT(L) 128-MBit Synchronous DRAM 14 ...
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... V. Pulse width measured at 50% points with amplitude measured peak to DC reference. Capacitance 3 Parameter Input Capacitance (CLK) Input Capacitance (A0 - A11, BA0, BA1, RAS, CAS, WE, CS, CKE, DQM) Input/Output Capacitance (DQ) INFINEON Technologies .............................................................................. – 0 4.6 V DDQ V = 3 DDQ Symbol ...
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... These parameters depend on the cycle rate. These values are measured at 133 MHz for -7 & -7.5 and at 100 MHz for -8 parts. Input signals are changed once during 6. These parameters are measured with continuous data stream during read access and all DQ toggling and assumed and the INFINEON Technologies HYB 39S128400/800/160CT(L) 128-MBit Synchronous DRAM 0.3 V Symb ...
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... Mode Register Set-up Time Power Down Mode Entry Time Common Parameters Row to Column Delay Time Row Precharge Time Row Active Time Row Cycle Time Activate(a) to Activate(b) Command Period CAS(a) to CAS(b) Command Period INFINEON Technologies t = 3 Symb. Limit Values -7 min. max. min. ...
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... AC timing tests have = 0.4 V and IL point. The transition time is measured between with the AC output load circuit shown in figure below. Specified T are measured with only, without any resistive termination and with a input signal edge rate between 0.8 V and 2.0 V. INFINEON Technologies 3 Symb. ...
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... Data out hold time toh is 1.8 ns for PC133 components with no termination and 0 pF load. 7. The write recovery time twr = 2 CLK cycles is a digital interlock on this device. Special devices with twr = 1 CLK for operations at less or equal 83 MHz will be available. INFINEON Technologies ...
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... Does not include plastic or metal protrusion of 0.15 max per side 2) Does not include plastic protrusion of 0.25 max per side 3) Does not include dambar protrusion of 0.13 max per side INFINEON Technologies HYB 39S128400/800/160CT(L) 128-MBit Synchronous DRAM 15˚ ±5˚ 15˚ ±5˚ ...
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... Random Row Write ( Interleaving Banks) with Precharge 18.1 CAS Latency = 2 18.2 CAS Latency = 3 19. Precharge Termination of a Burst 20. Full Page Burst Operation 20.1 Full Page Burst Read, CAS Latency = 2 18.2 Full Page Burst Write, CAS Latency = 3 INFINEON Technologies HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM 22 page 22 page 23 page 24 ...
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... NOP Activate "H" or "L" 2. Burst Read Operation (Burst Length = 4, CAS latency = CLK Command Read A NOP CAS latency = DQ’s CK2 CAS latency = DQ’s CK3 INFINEON Technologies T T Bank B Col. Addr. t RCD Write B NOP with Auto Precharge NOP NOP NOP DOUT A0 DOUT A1 DOUT A2 ...
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... DQ’s CK3 4. Read to Write Interval 4.1 Read to Write Interval (Burst Length = 4, CAS latency = CLK DQMx Command NOP Read A DQ’s "H" or "L" INFINEON Technologies NOP NOP NOP DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT A0 DOUT Minimum delay between the Read and Write ...
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... Non-Minimum Read to Write Interval (Burst Length = 4, CAS latency = CLK DQM Command NOP Read A CAS latency = DQ’s CK2 CAS latency = DQ’s CK3 "H" or "L" INFINEON Technologies DQW t DQZ 1 Clk Interval Bank A NOP Read A Write A Activate Must be Hi-Z before the Write Command DIN ...
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... Burst Write Operation (Burst Length = 4, CAS latency = CLK Command NOP Write A DQ’s DIN A0 The first data element and the Write are registered on the same clock edge. INFINEON Technologies NOP NOP NOP NOP don’t care DIN A1 DIN A2 DIN A3 Extra data is ignored after termination of a Burst ...
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... Write Interrupted by a Read (Burst Length = 4, CAS latency = CLK Command NOP Write A CAS latency = 2 DIN DQ’s CK2 CAS latency = 3 DIN DQ’s CK3 Input data for the Write is ignored. INFINEON Technologies Write B NOP NOP NOP DIN B0 DIN B1 DIN B2 DIN Read B NOP NOP NOP don’ ...
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... Command NOP Active DQ’s 7.2 Burst Read with Auto-Precharge (Burst Length = 4, CAS latency = CLK Read A Command NOP with AP CAS latency = 2 DQ’s CAS latency = 3 DQ’s INFINEON Technologies Write A NOP NOP NOP Auto Precharge DIN A0 DIN A1 Write A NOP NOP NOP Auto Precharge ...
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... RAS CAS RAx t AS Addr. RAx CAx DQM t RCD Hi-Z Ax0 Ax1 DQ Activate Command Bank A Write with Auto Precharge Command Bank A INFINEON Technologies T10 T11 T12 T13 Begin Auto Begin Auto Precharge Precharge Bank B Bank A RBx RAy RAy RAy RBx CBx ...
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... AC Parameters for a Read Timing CLK CK2 t CL CKE CKS RAS CAS RAx t AS Addr. RAx DQM Hi-Z DQ Activate Command Bank A INFINEON Technologies RBx CAx RBx t RRD t RAS AC2 AC2 RCD Ax0 Ax1 Activate Read with Read Command Command Auto Precharge Bank A Bank B ...
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... Mode Register Set CLK CKE CS RAS CAS Address Key Addr. Precharge Command All Banks Mode Register Set Command INFINEON Technologies T10 T11 T12 T13 t RSC Any Command 31 HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM CAS Latency = 2 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...
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... BS AP Addr. DQM t RP Hi-Z DQ Precharge Command All Banks Inputs must be 1st Auto Refresh stable for 200 s Command INFINEON Technologies T10 T11 T12 Minimum of 8 Refresh Cycles are required 8th Auto Refresh Command 32 HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM T13 T14 T15 T16 ...
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... T3 T4 CLK t CK2 CKE CS RAS CAS RAx Addr. RAx CAx DQM Hi-Z DQ Activate Read Command Command Bank A Bank A INFINEON Technologies T10 T11 T12 T13 t CSL t t CSL CSL Ax0 Ax1 Ax2 Ax3 Clock Clock Clock Suspend Suspend Suspend 1 Cycle 2 Cycles 3 Cycles ...
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... T3 T4 CLK t CK3 CKE CS RAS CAS RAx Addr. RAx CAx DQM Hi-Z DQ Activate Read Command Command Bank A Bank A INFINEON Technologies T10 T11 T12 T13 t CSL t t CSL CSL Ax0 Ax1 Ax2 Clock Clock Suspend Suspend 1 Cycle 2 Cycles 34 HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM ...
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... AP RAx Addr. RAx CAx DQM Hi-Z DQ DAx0 DAx1 Activate Clock Command Suspend Bank A 1 Cycle Write Command Bank A INFINEON Technologies T10 T11 T12 T13 DAx2 DAx3 Clock Clock Suspend Suspend 2 Cycles 3 Cycles 35 HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM Burst Length = 4, CAS Latency = 2 T14 ...
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... BA A8/AP RAx Addr. RAx CAx DQMx Hi-Z DQ DAx0 Activate Clock Command Suspend Bank A 1 Cycle Write Command Bank A INFINEON Technologies T10 T11 T12 T13 DAx1 DAx2 DAx3 Clock Clock Suspend Suspend 2 Cycles 3 Cycles 36 HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM Burst Length = 4, CAS Latency = 3 ...
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... CAS RAx Addr. RAx DQM Hi-Z DQ Activate Active Command Standby Bank A Clock Suspend Clock Suspend Mode Entry Mode Exit INFINEON Technologies T10 T11 T12 T13 CAx Ax0 Ax1 Ax2 Read Clock Mask Clock Mask Command Start End Bank A 37 HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM ...
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... CLK CKE t CKS CS RAS CAS Addr. DQM Hi-Z DQ All Banks Self Refresh must be idle Entry INFINEON Technologies T10 T11 T12 T13 t CKS t SREX Begin Self Refresh Exit Command Self Refresh Exit Self Refresh Command issued 38 HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM T14 T15 ...
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... T4 CLK t CK2 CKE CS RAS CAS Addr. t (Minimum Interval) RP DQM Hi-Z DQ Precharge Auto Refresh Command Command All Banks INFINEON Technologies T10 T11 T12 T13 Auto Refresh Command 39 HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM Burst Length = 4, CAS Latency = 2 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...
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... CK2 CKE CS RAS CAS RAw Addr. RAw CAw DQM Activate Read Command Command Bank A Bank A INFINEON Technologies T10 T11 T12 T13 CAx CAy Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Read Read Command Command Bank A Bank A 40 HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM ...
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... CLK t CK3 CKE CS RAS CAS RAw Addr. RAw CAw DQM Activate Read Command Command Bank A Bank A INFINEON Technologies T10 T11 T12 T13 CAx CAy Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Read Read Command Command Bank A Bank A 41 HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM ...
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... CK2 CKE CS RAS CAS RBw Addr. RBw CBw DQM DBw0 DBw1 DBw2 Activate Write Command Command Bank B Bank B INFINEON Technologies T10 T11 T12 T13 CBy CBx DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 Write Write Precharge Command Command Command Bank B Bank B ...
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... CK3 CKE CS RAS CAS RBz Addr. RBz CBz DQM DBw0 DBw1 DBw2 Activate Write Command Command Bank B Bank B INFINEON Technologies T10 T11 T12 T13 CBx CBy DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 Write Write Command Command Bank B Bank B 43 HYB39S128400/800/160CT(L) ...
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... RAS CAS RBx Addr. RBx CBx t RCD DQM t AC2 Hi-Z Bx0 Bx1 DQ Activate Read Command Command Bank B Bank B INFINEON Technologies T10 T11 T12 T13 RAx RBy RAx CAx RBy t RP Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Activate Precharge Activate ...
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... CK3 CKE High CS RAS CAS RBx Addr. RBx CBx t RCD DQM Hi-Z DQ Activate Read Command Command Bank B Bank B INFINEON Technologies T10 T11 T12 T13 RAx RAx CAx t AC3 Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Activate Read Precharge Command Command ...
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... CKE CS RAS CAS RAx Addr. RAx CAx t RCD DQM Hi-Z DQ DAx0 DAx1 DAx2 DAx3 Activate Write Command Command Bank A Bank A INFINEON Technologies T10 T11 T12 T13 RBx RAy RBx CBx RAy DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 Activate Write ...
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... RAS CAS RAx Addr. RAx CAx t RCD DQM Hi-Z DQ DAx0 DAx1 DAx2 Activate Write Command Command Bank A Bank A INFINEON Technologies T10 T11 T12 T13 T14 RBx RBx CBx t WR DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 Activate Write Precharge Command ...
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... CAS RAx Addr. RAx CAx DQM DAx0 DAx1 DAx2 Activate Write Command Command Bank A Bank A Precharge Termination of a Write Burst. Write Data is masked. INFINEON Technologies T10 T11 T12 RAy RAy CAy t RP DAx3 Ay0 Precharge Read Precharge Command Command Command Bank A ...
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... RAx RBx Addr. RAx CAx RBx DQM Hi Activate Read Activate Activate Command Command Command Command Bank A Bank A Bank B Bank B INFINEON Technologies T10 T11 T12 CBx + Bx+1 Bx+2 Read Command Bank B The burst counter wraps Full Page burst operation does not from the highest order terminate when the burst length is satisfied ...
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... CKE CS RAS CAS RAx Addr. RAx CAx DQM Hi-Z DQ Activate Activate Activate Command Command Command Bank A Bank B Bank B Read Command Bank A INFINEON Technologies T10 T11 T12 RBx RBx CBx Ax+ Ax Read Command Bank B The burst counter wraps Full Page burst operation does not from the highest order terminate when the burst length is satisfied ...
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... Precharge Command Burst Termination. Bank Selection by Address Bits Electrical Characteristics Absolute Maximum Ratings Recommended Operation and DC Characteristics Capacitance Operating Currents AC Characteristics Package Outlines. Table of Content. Timing DIagrams. INFINEON Technologies HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM page 1 page 2 page 2 page 3 page 4 page 4 page 5 page 6 page 7 ...
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... Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact INFINEON Technologies Offices in Munich or the INFINEON Technologies Sales Offices and Representatives worldwide. Due to technical requirements components may contain dangerous substances ...