FMS6419MSA28NL Fairchild Semiconductor, FMS6419MSA28NL Datasheet - Page 7

• Manufacturer Part Number: FMS6419MSA28NL
• Manufacturer: Fairchild Semiconductor

Specifications of FMS6419MSA28NL

• Lead Free Status / Rohs Status: Compliant

FMS6419
Applications
DC Levels
At any given time, the input signal’s DC levels must be
between 0.0V and 1.3V to utilize the optimal headroom and
to avoid clipping on the outputs. The Y channel should
nominally have the Sync Tip at ground and be a 1V signal.
The C channel should ride around the 0.5V level. This will
ensure that the filter will utilize the optimal headroom and
avoid clipping.
DC Coupled Output Applications
The 220 F capacitor coupled with the 150 termination
forms a high pass filter that blocks the DC while passing the
video frequencies and avoiding tilt. Lower values such as
Pin Configuration
Note:
Pin Assignments table follows on page 8.
REV. 5C April 2005
CV
AUX
IN
V
G
G
R
R
B
B
MUX
MUX
SSA
C
NC
NC
Y
INA
INB
INA
INB
INA
INB
IN
IN
IN
10
11
12
13
14
1
2
3
4
5
6
7
8
9
FMS6419MS28
28-pin SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
F
V
V
V
R
G
B
Y
V
C
CV
NC
V
NC
SEL
SSRGB
CCA
SS
OUT
OUT
OUT
CCO
OUT
SSYC
OUT
OUT
10 F would create a problem. By AC coupling, the average
DC level is zero. Thus, the output voltages of all channels
will be centered around zero. Alternately, DC coupling the
output of the FMS6419 is allowable, but not recommended.
There are several tradeoffs: The average DC level on the out-
puts will be 2V. Each output will dissipate an additional
40mW nominally. The application will need to accommodate
a 1V DC offset sync tip. Also, it is recommended to limit one
150 load per output.
Driving the Digital Pins with 3.3V
or 5V Logic
Either is allowed as long as the V
adhered to.
ih
and V
il
are
DATA SHEET
7