PI7C8150ND Pericom Semiconductor, PI7C8150ND Datasheet - Page 55

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PI7C8150ND

Manufacturer Part Number
PI7C8150ND
Description
Manufacturer
Pericom Semiconductor
Datasheet

Specifications of PI7C8150ND

Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Operating Temperature (max)
85C
Package Type
BGA
Rad Hardened
No
Case
BGA
Dc
04+
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PI7C8150ND
Quantity:
65
Part Number:
PI7C8150ND-33
Manufacturer:
SMD
Quantity:
626
Part Number:
PI7C8150ND-33
Manufacturer:
ALTERA
0
Table 6-2. Setting Secondary Interface Detected Parity Error Bit
Table 6-3. Setting Primary Interface Master Data Parity Error Detected Bit
Table 6–2 shows setting the detected parity error bit in the secondary status register,
corresponding to the secondary interface. This bit is set when PI7C8150 detects a parity
error on the secondary interface.
Table 6–3 shows setting data parity detected bit in the primary interface’s status register.
This bit is set under the following conditions:
!
!
!
0
1
0
0
0
X = don’t care
Secondary
Detected
Error Bit
0
1
0
0
0
0
0
1
0
0
0
1
X = don’t care
Primary
Parity Bit
0
0
1
0
0
0
1
0
0
0
1
0
X = don’t care
PI7C8150 must be a master on the primary bus.
The parity error response bit in the command register, corresponding to the primary
interface, must be set.
The P_PERR_L signal is detected asserted or a parity error is detected on the primary
bus.
Parity
Data
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
45
Direction
Downstream
Upstream
Direction
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
March 19, 2003 – Revision 1.04
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Bus Where Error
Bus Where Error
2-PORT PCI-TO-PCI BRIDGE
Was Detected
Was Detected
ADVANCE INFORMATION
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
1 / x
x / x
x / x
x / x
1 / x
x / x
x / x
x / x
1 / x
x / x
Secondary Parity
Secondary Parity
Error Response
Error Response
Primary /
Primary/
Bits
Bits
PI7C8150

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