PI7C8150ND Pericom Semiconductor, PI7C8150ND Datasheet - Page 26

• Manufacturer Part Number: PI7C8150ND
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150ND

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Case: BGA
• Dc: 04+
• Lead Free Status / Rohs Status: Not Compliant

3.6.2
3.6.3
Table 4-4. Read Prefetch Address Boundaries
However, byte enable bits cannot be forwarded for all data phases as is done for the single
data phase of the non-prefetchable read transaction. For prefetchable read transactions,
PI7C8150 forces all byte enable bits to be turned on for all data phases.
Prefetchable behavior is used for memory read line and memory read multiple transactions,
as well as for memory read transactions that fall into prefetchable memory space.
The amount of data that is pre-fetched depends on the type of transaction.
The amount of pre-fetching may also be affected by the amount of free buffer
space available in PI7C8150, and by any read address boundaries encountered.
Pre-fetching should not be used for those read transactions that have side effects in the
target device, that is, control and status registers, FIFO’s, and so on.
The target device’s base address register or registers indicate if a memory address region is
prefetchable.
NON-PREFETCHABLE READ TRANSACTIONS
A non-prefetchable read transaction is a read transaction where PI7C8150 requests one and
only one DWORD from the target and disconnects the initiator after delivery of the first
DWORD of read data. Unlike prefetchable read transactions, PI7C8150 forwards the read
byte enable information for the data phase.
Non-prefetchable behavior is used for I/O and configuration read transactions,
as well as for memory read transactions that fall into non-prefetchable memory space.
If extra read transactions could have side effects, for example, when accessing a FIFO, use
non-prefetchable read transactions to those locations. Accordingly, if it is important to
retain the value of the byte enable bits during the data phase, use non-prefetchable read
transactions. If these locations are mapped in memory space, use the memory read
command and map the target into non-prefetchable (memory-mapped I/O) memory space
to use non-prefetching behavior.
READ PREFETCH ADDRESS BOUNDARIES
PI7C8150 imposes internal read address boundaries on read pre-fetched data. When a read
transaction reaches one of these aligned address boundaries, the PI7C8150 stops pre-
fetched data, unless the target signals a target disconnect before the read pre-fetched
boundary is reached. When PI7C8150 finishes transferring this read data to the initiator, it
returns a target disconnect with the last data transfer, unless the initiator completes the
transaction before all pre-fetched read data is delivered. Any leftover pre-fetched data is
discarded.
Prefetchable read transactions in flow-through mode pre-fetch to the nearest aligned 4KB
address boundary, or until the initiator de-asserts FRAME_L. Section 3.6.6 describes flow-
through mode during read operations.
Table 4-4 shows the read pre-fetch address boundaries for read transactions during non-
flow-through mode.
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March 19, 2003 – Revision 1.04
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
PI7C8150