PI7C8150ND Pericom Semiconductor, PI7C8150ND Datasheet - Page 48

• Manufacturer Part Number: PI7C8150ND
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150ND

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Case: BGA
• Dc: 04+
• Lead Free Status / Rohs Status: Not Compliant

6
6.1
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PI7C8150 does not have a hardware mechanism to guarantee data synchronization for
posted write transactions. Therefore, all posted write transactions must be followed by a
read operation, either from the device to the location just written (or some other location
along the same path), or from the device driver to one of the device registers.
ERROR HANDLING
PI7C8150 checks, forwards, and generates parity on both the primary and secondary
interfaces. To maintain transparency, PI7C8150 always tries to forward the existing parity
condition on one bus to the other bus, along with address and data. PI7C8150 always
attempts to be transparent when reporting errors, but this is not always possible, given the
presence of posted data and delayed transactions.
To support error reporting on the PCI bus, PI7C8150 implements the following:
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This chapter provides detailed information about how PI7C8150 handles errors.
It also describes error status reporting and error operation disabling.
ADDRESS PARITY ERRORS
PI7C8150 checks address parity for all transactions on both buses, for all address and all
bus commands. When PI7C8150 detects an address parity error on the primary interface,
the following events occur:
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!
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The device signaling the interrupt performs a read of the data just written (software).
The device driver performs a read operation to any register in the interrupting device
before accessing data written by the device (software).
System hardware guarantees that write buffers are flushed before interrupts are
forwarded.
PERR_L and SERR_L signals on both the primary and secondary interfaces
Primary status and secondary status registers
The device-specific P_SERR_L event disable register
If the parity error response bit is set in the command register, PI7C8150 does not claim
the transaction with P_DEVSEL_L; this may allow the transaction to terminate in a
master abort. If parity error response bit is not set, PI7C8150 proceeds normally and
accepts the transaction if it is directed to or across PI7C8150.
PI7C8150 sets the detected parity error bit in the status register.
PI7C8150 asserts P_SERR_L and sets signaled system error bit in the status register, if
both the following conditions are met:
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The SERR_L enable bit is set in the command register.
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March 19, 2003 – Revision 1.04
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
PI7C8150